dsPIC33FJ32GP104-I/PT Microchip Technology, dsPIC33FJ32GP104-I/PT Datasheet - Page 99

• Manufacturer Part Number: dsPIC33FJ32GP104-I/PT
• Description: Digital Signal Processors & Controllers - DSP, DSC 16bit Gen Prp Fam16 MIPS 32KBFLSH 2KBRAM
• Manufacturer: Microchip Technology
• Type: dsPIC33FJ32(GP/MC)101/102/104r

Specifications of dsPIC33FJ32GP104-I/PT

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 16 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33FJ32(GP/MC)101/102/104
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

REGISTER 7-1:
REGISTER 7-2:
 2011-2012 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
Note 1:
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 3
Note 1:
R/W-0
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
IPL2
R/W-0
SATA
R-0
U-0
OA
—
2:
3:
2:
(2)
(3)
For complete register details, see
The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
For complete register details, see
The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
IPL<2:0>: CPU Interrupt Priority Level Status bits
111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
IPL3: CPU Interrupt Priority Level Status bit 3
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
R/W-0
IPL1
R/W-0
SATB
R-0
U-0
OB
—
SR: CPU STATUS REGISTER
CORCON: CORE CONTROL REGISTER
(2)
(3)
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R/W-0
SATDW
IPL0
R/W-1
R/C-0
U-0
SA
—
(2)
(3)
Register
Register
ACCSAT
R/W-0
R/W-0
R/C-0
R-0
SB
RA
US
3-1.
3-2.
(1)
‘0’ = Bit is cleared
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
(2)
IPL3
R/W-0
R/W-0
R/C-0
OAB
EDT
R-0
N
(2,3)
(2)
(1)
R/W-0
R/W-0
R/C-0
SAB
PSV
R-0
OV
x = Bit is unknown
x = Bit is unknown
DL<2:0>
R/W-0
R/W-0
RND
R-0
R-0
DA
Z
DS70652E-page 99
R/W-0
R/W-0
R/W-0
R-0
DC
IF
C
bit 8
bit 0
bit 8
bit 0