dsPIC33FJ32GP104-I/PT Microchip Technology, dsPIC33FJ32GP104-I/PT Datasheet - Page 201

• Manufacturer Part Number: dsPIC33FJ32GP104-I/PT
• Description: Digital Signal Processors & Controllers - DSP, DSC 16bit Gen Prp Fam16 MIPS 32KBFLSH 2KBRAM
• Manufacturer: Microchip Technology
• Type: dsPIC33FJ32(GP/MC)101/102/104r

Specifications of dsPIC33FJ32GP104-I/PT

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 16 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33FJ32(GP/MC)101/102/104
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

17.0
The Inter-Integrated Circuit™ (I
complete hardware support for both Slave and Multi-
Master modes of the I
standard, with a 16-bit interface.
The I
• The SCLx pin is clock
• The SDAx pin is data
The I
• I
• I
• I
• I
• Serial clock synchronization for I
• I
 2011-2012 Microchip Technology Inc.
modes of operation.
master and slaves
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control)
collision and arbitrates accordingly
2
2
2
2
2
Note 1: This data sheet summarizes the features
C interface supporting both Master and Slave
C Slave mode supports 7-bit and 10-bit addresses
C Master mode supports 7-bit and 10-bit addresses
C port allows bidirectional transfers between
C supports multi-master operation, detects bus
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
2
2
C module has a 2-pin interface:
C module offers the following key features:
2: Some registers and associated bits
INTER-INTEGRATED CIRCUIT™
(I
2
C™)
of the dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 family
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to Section 19. “Inter-Integrated
Circuit™ (I
“dsPIC33F/PIC24H
Manual”, which is available from the
Microchip web site (www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
2
C™)” (DS70195) in the
2
C serial communication
2
C™) module provides
Family
2
C port can be
Reference
in
17.1
The hardware fully implements all the master and slave
functions of the I
specifications, as well as 7-bit and 10-bit addressing.
The I
master on an I
The following types of I
• I
• I
• I
For details about the communication sequence in each
of these modes, refer to the Microchip web site
(www.microchip.com) for the latest “dsPIC33F/PIC24H
Family Reference Manual” sections.
17.2
I2CxCON and I2CxSTAT are control and status
registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CxSTAT are
read/write:
• I2CxRSR is the shift register used for shifting data
• I2CxRCV is the receive buffer and the register to
• I2CxTRN is the transmit register to which bytes
• I2CxADD register holds the slave address
• ADD10 status bit indicates 10-Bit Addressing
• I2CxBRG acts as the Baud Rate Generator (BRG)
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV
and an interrupt pulse is generated.
which data bytes are written or from which data
bytes are read
are written during a transmit operation
mode
reload value
2
2
2
C slave operation with 7-bit address
C slave operation with 10-bit address
C master operation with 7-bit or 10-bit address
2
C module can operate either as a slave or a
Operating Modes
I
2
C Registers
2
C bus.
2
C Standard and Fast mode
2
C operation are supported:
DS70652E-page 201