dsPIC33FJ32GP104-I/PT Microchip Technology, dsPIC33FJ32GP104-I/PT Datasheet - Page 91

• Manufacturer Part Number: dsPIC33FJ32GP104-I/PT
• Description: Digital Signal Processors & Controllers - DSP, DSC 16bit Gen Prp Fam16 MIPS 32KBFLSH 2KBRAM
• Manufacturer: Microchip Technology
• Type: dsPIC33FJ32(GP/MC)101/102/104r

Specifications of dsPIC33FJ32GP104-I/PT

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 16 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33FJ32(GP/MC)101/102/104
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

FIGURE 6-2:
TABLE 6-2:
 2011-2012 Microchip Technology Inc.
V
T
V
T
T
T
Symbol
POR
BOR
PWRT
FSCM
POR
BOR
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Oscillator Clock
1.
2.
3.
4.
5.
6.
Device Status
POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until V
V
BOR: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until V
delay, T
PWRT Timer: The Power-up Timer continues to hold the processor in Reset for a specific period of time (T
delay, T
T
Oscillator Delay: The total delay for the clock to be ready for various clock source selections is given in
Section 8.0 “Oscillator Configuration”
When the oscillator clock is ready, the processor begins execution from location, 0x000000. The user application programs a GOTO
instruction at the Reset address, which redirects program execution to the appropriate start-up routine.
The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is ready and the delay,
T
SYSRST
PWRT
FSCM
POR
POR Extension Time 30 s maximum
BOR Extension Time 100 s maximum
FSCM
POR
BOR
POR Threshold
BOR Threshold
Power-up Time
Fail-Safe Clock
V
threshold and the delay, T
Monitor Delay
, has elapsed.
, has elapsed, the SYSRST becomes inactive, which in turn, enables the selected oscillator to start generating clock cycles.
DD
PWRT
BOR
Parameter
OSCILLATOR PARAMETERS
Delay
, has elapsed. The delay, T
, ensures that the system power supplies have stabilized at the appropriate level for full-speed operation. After the delay,
1
SYSTEM RESET TIMING
2
T
1.8V nominal
2.5V nominal
64 ms nominal
900 s maximum
POR
V
POR
POR
, has elapsed.
BOR
Value
for more information.
, ensures the voltage regulator output becomes stable.
V
BOR
T
T
PWRT
BOR
3
Reset
Time
Note:
T
OSCD
When the device exits the Reset condition
(begins normal operation), the device
operating parameters (voltage, frequency,
temperature, etc.) must be within their
operating ranges; otherwise, the device
may not function correctly. The user appli-
cation must ensure that the delay between
the time power is first applied, and the time
SYSRST becomes inactive, is long
enough to get all operating parameters
within specification.
T
OST
DD
4
crosses the V
T
LOCK
PWRT
BOR
Table
) after a BOR. The
threshold and the
DD
DS70652E-page 91
6-1. Refer to
5
crosses the
6
Run
T
FSCM