dsPIC33FJ32GP104-I/PT Microchip Technology, dsPIC33FJ32GP104-I/PT Datasheet - Page 92

• Manufacturer Part Number: dsPIC33FJ32GP104-I/PT
• Description: Digital Signal Processors & Controllers - DSP, DSC 16bit Gen Prp Fam16 MIPS 32KBFLSH 2KBRAM
• Manufacturer: Microchip Technology
• Type: dsPIC33FJ32(GP/MC)101/102/104r

Specifications of dsPIC33FJ32GP104-I/PT

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 16 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33FJ32(GP/MC)101/102/104
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
6.3
A POR circuit ensures the device is reset from power-
on. The POR circuit is active until V
V
delay, T
circuits become stable.
The device supply voltage characteristics must meet
the specified starting voltage and rise rate require-
ments to generate the POR. Refer to
“Electrical Characteristics”
The POR status (POR) bit in the Reset Control
(RCON<0>) register is set to indicate the Power-on
Reset.
FIGURE 6-3:
DS70652E-page 92
POR
threshold and the delay, T
POR
POR
, ensures that the internal device bias
SYSRST
SYSRST
SYSRST
V
V
V
DD
DD
DD
BROWN-OUT RESET SITUATIONS
V
DD
for details.
Dips Before PWRT Expires
POR
, has elapsed. The
DD
Section 26.0
crosses the
T
BOR
6.4
The on-chip regulator has a BOR circuit that resets the
device when the V
device operation. The BOR circuit keeps the device in
Reset until V
delay, T
the voltage regulator output becomes stable.
The BOR status (BOR) bit in the Reset Control
(RCON<1>) register is set to indicate the Brown-out
Reset.
The device will not run at full speed after a BOR as the
V
operation. The Power-up Timer (PWRT) provides
power-up time delay (T
power supplies have stabilized at the appropriate levels
for full-speed operation before the SYSRST is
released.
Refer to
details.
Figure 6-3
Reset delay (T
rises above the V
+ T
DD
T
PWRT
T
BOR
should rise to acceptable levels for full-speed
BOR
BOR
BOR and PWRT
Section 23.0 “Special Features”
+ T
+ T
shows the typical brown-out scenarios. The
PWRT
, has elapsed. The delay, T
PWRT
DD
BOR
crosses the V
BOR
DD
 2011-2012 Microchip Technology Inc.
+ T
is too low (V
trip point.
PWRT
PWRT
) is initiated each time V
) to ensure that the system
BOR
DD
V
V
V
< V
threshold and the
BOR
BOR
BOR
BOR
BOR
) for proper
for further
, ensures
DD