dsPIC33FJ32GP104-I/PT Microchip Technology, dsPIC33FJ32GP104-I/PT Datasheet - Page 93

• Manufacturer Part Number: dsPIC33FJ32GP104-I/PT
• Description: Digital Signal Processors & Controllers - DSP, DSC 16bit Gen Prp Fam16 MIPS 32KBFLSH 2KBRAM
• Manufacturer: Microchip Technology
• Type: dsPIC33FJ32(GP/MC)101/102/104r

Specifications of dsPIC33FJ32GP104-I/PT

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 16 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33FJ32(GP/MC)101/102/104
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

6.5
The External Reset is generated by driving the MCLR
pin low. The MCLR pin is a Schmitt trigger input with an
additional glitch filter. Reset pulses that are longer than
the minimum pulse width will generate a Reset. Refer
to
minimum pulse-width specifications. The External
Reset (MCLR) Pin (EXTR) bit in the Reset Control
(RCON) register is set to indicate the MCLR Reset.
6.5.1
Many systems have external supervisory circuits that
generate Reset signals to reset multiple devices in the
system. This External Reset signal can be directly con-
nected to the MCLR pin to reset the device when the
rest of the system is reset.
6.5.2
When using the internal power supervisory circuit to
reset the device, the External Reset pin (MCLR) should
be tied directly or resistively to V
MCLR pin will not be used to generate a Reset. The
External Reset pin (MCLR) does not have an internal
pull-up and must not be left unconnected.
6.6
Whenever the RESET instruction is executed, the device
will assert SYSRST, placing the device in a special
Reset state. This Reset state will not re-initialize the
clock. The clock source in effect prior to the RESET
instruction will remain as the source. SYSRST is
released at the next instruction cycle and the Reset
vector fetch will commence.
The Software Reset (Instruction) Flag (SWR) bit in the
Reset Control (RCON<6>) register is set to indicate the
Software Reset.
6.7
Whenever a Watchdog Timer Time-out Reset occurs,
the device will asynchronously assert SYSRST. The
clock source will remain unchanged. A WDT time-out
during Sleep or Idle mode will wake-up the processor,
but will not reset the processor.
The Watchdog Timer Time-out Flag (WDTO) bit in the
Reset Control (RCON<4>) register is set to indicate the
Watchdog Reset. Refer to
Timer (WDT)”
Reset.
 2011-2012 Microchip Technology Inc.
Section 26.0 “Electrical Characteristics”
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
External Reset (EXTR)
Software RESET Instruction (SWR)
Watchdog Timer Time-out Reset
(WDTO)
EXTERNAL SUPERVISORY
CIRCUIT
INTERNAL SUPERVISORY CIRCUIT
for more information on Watchdog
Section 23.4 “Watchdog
DD
. In this case, the
for
6.8
If a lower priority hard trap occurs while a higher priority
trap is being processed, a hard Trap Conflict Reset
occurs. The hard traps include exceptions of Priority
Level 13 through Level 15, inclusive. The address error
(Level 13) and oscillator error (Level 14) traps fall into
this category.
The Trap Reset Flag (TRAPR) bit in the Reset Control
(RCON<15>) register is set to indicate the Trap Conflict
Reset. Refer to
more information on Trap Conflict Resets.
6.9
To maintain the integrity of the Peripheral Pin Select
Control registers, they are constantly monitored with
shadow registers in hardware. If an unexpected
change in any of the registers occurs (such as cell
disturbances caused by ESD or other external events),
a Configuration Mismatch Reset occurs.
The Configuration Mismatch Flag (CM) bit in the Reset
Control (RCON<9>) register is set to indicate the
Configuration Mismatch Reset. Refer to
“I/O Ports”
Mismatch Reset.
6.10
An Illegal Condition Device Reset occurs due to the
following sources:
• Illegal Opcode Reset
• Uninitialized W Register Reset
• Security Reset
The Illegal Opcode or Uninitialized W Access Reset
Flag (IOPUWR) bit in the Reset Control (RCON<14>)
register is set to indicate the Illegal Condition Device
Reset.
6.10.1
A device Reset is generated if the device attempts to
execute an illegal opcode value that is fetched from
program memory.
The Illegal Opcode Reset function can prevent the
device from executing program memory sections that
are used to store constant data. To take advantage of
the Illegal Opcode Reset, use only the lower 16 bits of
each program memory section to store the data values.
The upper 8 bits should be programmed with 0x3F,
which is an illegal opcode value.
Note:
Trap Conflict Reset
Configuration Mismatch Reset
Illegal Condition Device Reset
The Configuration Mismatch feature and
associated Reset flag is not available on
all devices.
ILLEGAL OPCODE RESET
for more information on the Configuration
Section 7.0 “Interrupt Controller”
DS70652E-page 93
Section 10.0
for