PIC18F27J13-I/SP Microchip Technology, PIC18F27J13-I/SP Datasheet - Page 131

• Manufacturer Part Number: PIC18F27J13-I/SP
• Description: IC PIC MCU 128KB FLASH 28SPDIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J13-I/SP

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Controller Family/series: PIC18
• Cpu Speed: 48MHz
• Digital Ic Case Style: DIP
• Supply Voltage Range: 1.8V To 5.5V
• Embedded Interface Type: I2C, SPI, USART
• Rohs Compliant: Yes
• Core: PIC
• Processor Series: PIC18F
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 48 MHz
• Data Ram Size: 3.76 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 2
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• A/d Bit Size: 12 bit
• A/d Channels Available: 10
• Height: 3.43 mm
• Interface Type: I2C, SPI, USART
• Length: 34.4 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.15 V
• Width: 7.24 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180030 - BOARD DEMO PIC18F47J13 FS USBMA180029 - BOARD DEMO PIC18F47J53 FS USB
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

9.8
External interrupts on the RB0/INT0, RB1/INT1 and
RB2/INT2 pins are edge-triggered. If the corresponding
INTEDGx bit in the INTCON2 register is set (= 1), the
interrupt is triggered by a rising edge; if the bit is clear,
the trigger is on the falling edge. When a valid edge
appears on the RBx/INTx pin, the corresponding flag
bit, INTxF, is set. This interrupt can be disabled by
clearing the corresponding enable bit, INTxE. Flag bit,
INTxF, must be cleared by software in the Interrupt
Service Routine before re-enabling the interrupt.
All external interrupts (INT0, INT1 and INT2) can wake-
up the processor from Idle or Sleep modes if bit INTxE
was set prior to going into those modes. If the Global
Interrupt Enable bit, GIE/GIEH, is set, the processor
will branch to the interrupt vector following wake-up.
Interrupt priority for INT1 and INT2 is determined by
the value contained in the interrupt priority bits, INT1IP
and INT2IP of the INTCON3 register. There is no prior-
ity bit associated with INT0. It is always a high priority
interrupt source.
EXAMPLE 9-1:
 2010 Microchip Technology Inc.
MOVWF
MOVFF
MOVFF
;
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
INTn Pin Interrupts
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
Preliminary
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
; Restore BSR
; Restore WREG
; Restore STATUS
9.9
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh  00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L regis-
ter pair (FFFFh 0000h) will set TMR0IF. The interrupt
can be enabled/disabled by setting/clearing enable bit,
TMR0IE of the INTCON register. Interrupt priority for
Timer0 is determined by the value contained in the
interrupt priority bit, TMR0IP of the INTCON2 register.
See
on the Timer0 module.
9.10
An input change on PORTB<7:4> sets flag bit, RBIF of
the INTCON register. The interrupt can be enabled/
disabled by setting/clearing enable bit, RBIE of the
INTCON register. Pins must also be individually
enabled with the IOCB register. Interrupt priority for
PORTB interrupt-on-change is determined by the value
contained in the interrupt priority bit, RBIP of the
INTCON2 register.
9.11
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the fast return stack. If a fast
return from interrupt is not used (see
“Fast Register
WREG, STATUS and BSR registers on entry to the
Interrupt Service Routine. Depending on the user’s
application, other registers may also need to be saved.
Example 9-1
and BSR registers during an Interrupt Service Routine.
PIC18(L)F2X/4XK22
Section 11.0 “Timer0 Module”
TMR0 Interrupt
PORTB Interrupt-on-Change
Context Saving During Interrupts
saves and restores the WREG, STATUS
Stack”), the user may need to save the
DS41412D-page 131
for further details
Section 5.1.3