PIC18F27J13-I/SP Microchip Technology, PIC18F27J13-I/SP Datasheet - Page 166

• Manufacturer Part Number: PIC18F27J13-I/SP
• Description: IC PIC MCU 128KB FLASH 28SPDIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J13-I/SP

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Controller Family/series: PIC18
• Cpu Speed: 48MHz
• Digital Ic Case Style: DIP
• Supply Voltage Range: 1.8V To 5.5V
• Embedded Interface Type: I2C, SPI, USART
• Rohs Compliant: Yes
• Core: PIC
• Processor Series: PIC18F
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 48 MHz
• Data Ram Size: 3.76 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 2
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• A/d Bit Size: 12 bit
• A/d Channels Available: 10
• Height: 3.43 mm
• Interface Type: I2C, SPI, USART
• Length: 34.4 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.15 V
• Width: 7.24 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180030 - BOARD DEMO PIC18F47J13 FS USBMA180029 - BOARD DEMO PIC18F47J53 FS USB
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18(L)F2X/4XK22
12.8
The
increments to FFFFh and rolls over to 0000h. When
Timer1/3/5 rolls over, the Timer1/3/5 interrupt flag bit of
the PIR1/2/5 register is set. To enable the interrupt on
rollover, you must set these bits:
• TMRxON bit of the TxCON register
• TMRxIE bits of the PIE1, PIE2 or PIE5 registers
• PEIE/GIEL bit of the INTCON register
• GIE/GIEH bit of the INTCON register
The interrupt is cleared by clearing the TMRxIF bit in
the Interrupt Service Routine.
For more information on selecting high or low priority
status for the Timer1/3/5 Overflow Interrupt, see
Section 9.0
12.9
Timer1/3/5 can only operate during Sleep when set up
in Asynchronous Counter mode. In this mode, an
external crystal or clock source can be used to
increment the counter. To set up the timer to wake the
device:
• TMRxON bit of the TxCON register must be set
• TMRxIE bit of the PIE1/2/5 register must be set
• PEIE/GIEL bit of the INTCON register must be set
• TxSYNC bit of the TxCON register must be set
• TMRxCS bits of the TxCON register must be
• TxSOSCEN bit of the TxCON register must be
The device will wake-up on an overflow and execute
the next instruction. If the GIE/GIEH bit of the INTCON
register is set, the device will call the Interrupt Service
Routine.
The secondary oscillator will continue to operate in
Sleep regardless of the TxSYNC bit setting.
DS41412D-page 166
Note:
configured
configured
Timer1/3/5
Timer1/3/5 Interrupt
Timer1/3/5 Operation During Sleep
The TMRxH:TMRxL register pair and the
TMRxIF bit should be cleared before
enabling interrupts.
“Interrupts”.
register
pair
(TMRxH:TMRxL)
Preliminary
12.10 ECCP/CCP Capture/Compare Time
The CCP modules use the TMRxH:TMRxL register pair
as the time base when operating in Capture or
Compare mode.
In Capture mode, the value in the TMRxH:TMRxL
register pair is copied into the CCPRxH:CCPRxL
register pair on a configured event.
In Compare mode, an event is triggered when the value
CCPRxH:CCPRxL register pair matches the value in
the TMRxH:TMRxL register pair. This event can be a
Special Event Trigger.
For
“Capture/Compare/PWM Modules”.
12.11 ECCP/CCP Special Event Trigger
When any of the CCP’s are configured to trigger a
special event, the trigger will clear the TMRxH:TMRxL
register pair. This special event does not cause a
Timer1/3/5 interrupt. The CCP module may still be
configured to generate a CCP interrupt.
In this mode of operation, the CCPRxH:CCPRxL
register pair
Timer1/3/5.
Timer1/3/5 should be synchronized and F
be selected as the clock source in order to utilize the
Special Event Trigger. Asynchronous operation of
Timer1/3/5 can cause a Special Event Trigger to be
missed.
In the event that a write to TMRxH or TMRxL coincides
with a Special Event Trigger from the CCP, the write will
take precedence.
For more information, see Section 17.2.8 “Special
Event Trigger”.
more
Base
becomes the
information,
 2010 Microchip Technology Inc.
period
see
Section 14.0
OSC
register
/4 should
for