PIC18F27J13-I/SP Microchip Technology, PIC18F27J13-I/SP Datasheet - Page 210
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PIC18F27J13-I/SP
Manufacturer Part Number
PIC18F27J13-I/SP
Description
IC PIC MCU 128KB FLASH 28SPDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F26J13-ISS.pdf
(558 pages)
4.PIC18F26J13-ISS.pdf
(12 pages)
Specifications of PIC18F27J13-I/SP
Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Controller Family/series
PIC18
Cpu Speed
48MHz
Digital Ic Case Style
DIP
Supply Voltage Range
1.8V To 5.5V
Embedded Interface Type
I2C, SPI, USART
Rohs Compliant
Yes
Core
PIC
Processor Series
PIC18F
Data Bus Width
8 bit
Maximum Clock Frequency
48 MHz
Data Ram Size
3.76 KB
On-chip Adc
Yes
Number Of Programmable I/os
2
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
A/d Bit Size
12 bit
A/d Channels Available
10
Height
3.43 mm
Interface Type
I2C, SPI, USART
Length
34.4 mm
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.15 V
Width
7.24 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180030 - BOARD DEMO PIC18F47J13 FS USBMA180029 - BOARD DEMO PIC18F47J53 FS USB
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- PIC18LF24J10-ISS PDF datasheet
- PIC18F26J13-ISS PDF datasheet #2
- PIC18F26J13-ISS PDF datasheet #3
- PIC18F26J13-ISS PDF datasheet #4
- Current page: 210 of 496
- Download datasheet (5Mb)
PIC18(L)F2X/4XK22
15.2
The Serial Peripheral Interface (SPI) bus is a
synchronous serial data communication bus that
operates in Full-Duplex mode. Devices communicate
in a master/slave environment where the master device
initiates the communication. A slave device is
controlled through a chip select known as Slave Select.
The SPI bus specifies four signal connections:
• Serial Clock (SCKx)
• Serial Data Out (SDOx)
• Serial Data In (SDIx)
• Slave Select (SSx)
Figure 15-1
module when operating in SPI Mode.
The SPI bus operates with a single master device and
one or more slave devices. When multiple slave
devices are used, an independent Slave Select
connection is required from the master device to each
slave device.
Figure 15-4
master device and multiple slave devices.
The master selects only one slave at a time. Most slave
devices have tri-state outputs so their output signal
appears disconnected from the bus when they are not
selected.
Transmissions involve two shift registers, eight bits in
size, one in the master and one in the slave. With either
the master or the slave device, data is always shifted
out one bit at a time, with the Most Significant bit (MSb)
shifted out first. At the same time, a new Least
Significant bit (LSb) is shifted into the same register.
Figure 15-5
processors configured as master and slave devices.
Data is shifted out of both shift registers on the
programmed clock edge and latched on the opposite
edge of the clock.
The master device transmits information out on its
SDOx output pin which is connected to, and received
by, the slave’s SDIx input pin. The slave device trans-
mits information out on its SDOx output pin, which is
connected to, and received by, the master’s SDIx input
pin.
To begin communication, the master device first sends
out the clock signal. Both the master and the slave
devices should be configured for the same clock
polarity.
The master device starts a transmission by sending out
the MSb from its shift register. The slave device reads
this bit from that same line and saves it into the LSb
position of its shift register.
DS41412D-page 210
SPI Mode Overview
shows the block diagram of the MSSPx
shows a typical connection between two
shows a typical connection between a
Preliminary
During each SPI clock cycle, a full-duplex data
transmission occurs. This means that at the same time,
the slave device is sending out the MSb from its shift
register and the master device is reading this bit from
that same line and saving it as the LSb of its shift
register.
After 8 bits have been shifted out, the master and slave
have exchanged register values.
If there is more data to exchange, the shift registers are
loaded with new data and the process repeats itself.
Whether the data is meaningful or not (dummy data),
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends useful data and slave sends
• Master sends useful data and slave sends useful
• Master sends dummy data and slave sends use-
Transmissions may involve any number of clock
cycles. When there is no more data to be transmitted,
the master stops sending the clock signal and it
deselects the slave.
Every slave device connected to the bus that has not
been selected through its slave select line must disre-
gard the clock and transmission signals and must not
transmit out any data of its own.
dummy data.
data.
ful data.
2010 Microchip Technology Inc.
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