PIC18F27J13-I/SP Microchip Technology, PIC18F27J13-I/SP Datasheet - Page 161

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PIC18F27J13-I/SP

Manufacturer Part Number
PIC18F27J13-I/SP
Description
IC PIC MCU 128KB FLASH 28SPDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18F27J13-I/SP

Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Controller Family/series
PIC18
Cpu Speed
48MHz
Digital Ic Case Style
DIP
Supply Voltage Range
1.8V To 5.5V
Embedded Interface Type
I2C, SPI, USART
Rohs Compliant
Yes
Core
PIC
Processor Series
PIC18F
Data Bus Width
8 bit
Maximum Clock Frequency
48 MHz
Data Ram Size
3.76 KB
On-chip Adc
Yes
Number Of Programmable I/os
2
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
A/d Bit Size
12 bit
A/d Channels Available
10
Height
3.43 mm
Interface Type
I2C, SPI, USART
Length
34.4 mm
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.15 V
Width
7.24 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180030 - BOARD DEMO PIC18F47J13 FS USBMA180029 - BOARD DEMO PIC18F47J53 FS USB
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
12.0
The Timer1/3/5 module is a 16-bit timer/counter with
the following features:
• 16-bit timer/counter register pair (TMRxH:TMRxL)
• Programmable internal or external clock source
• 2-bit prescaler
• Dedicated Secondary 32 kHz oscillator circuit
• Optionally synchronized comparator out
• Multiple Timer1/3/5 gate (count enable) sources
• Interrupt on overflow
• Wake-up on overflow (external clock,
• 16-Bit Read/Write Operation
• Time base for the Capture/Compare function
FIGURE 12-1:
 2010 Microchip Technology Inc.
Timer2/4/6 Match
Asynchronous mode only)
SYNCC2OUT
PR2/4/6
SYNCC1OUT
Comparator 2
Comparator 1
TxG
TxGSS<1:0>
TIMER1/3/5 MODULE WITH
GATE CONTROL
Note 1:
(7)
(7)
2:
3:
4:
5:
6:
7:
TxCKI
TxGPOL
Set flag bit
TMRxIF on
Overflow
ST Buffer is high speed type when using TxCKI.
Timer1/3/5 register increments on rising edge.
Synchronize does not operate while in Sleep.
See
T1CKI is not available when the secondary oscillator is enabled. (SOSCGO = 1 or TXSOSCEN = 1)
T3CKI is not available when the secondary oscillator is enabled, unless T3CMX = 1.
Synchronized comparator output should not be used in conjunction with synchronized TxCKI.
Secondary
Oscillator
Module
See Figure 2-4
00
10
11
TIMER1/3/5 BLOCK DIAGRAM
01
Figure 12-2
(5)
TxSOSCEN
,(6)
TMRxON
TxGTM
TMRxH
for 16-Bit Read/Write Mode Block Diagram.
SOSCOUT
TMRx
(1)
TxG_IN
(2),(4)
D
R
CK
TMRxL
1
0
Q
Q
TxCLK_EXT_SRC
Preliminary
TMRxCS<1:0>
0
1
Reserved
TxGGO/DONE
Q
Internal
Internal
F
OSC
Clock
Clock
F
OSC
EN
/4
D
• Special Event Trigger (with CCP/ECCP)
• Selectable Gate Source Polarity
• Gate Toggle Mode
• Gate Single-pulse Mode
• Gate Value Status
• Gate Event Interrupt
Figure 12-1
module.
TxCLK
Single Pulse
Acq. Control
11
10
01
00
PIC18(L)F2X/4XK22
TxGSPM
TxCKPS<1:0>
TxSYNC
Prescaler
1, 2, 4, 8
TMRxON
is a block diagram of the Timer1/3/5
0
1
2
0
1
Internal
F
Clock
TxGVAL
OSC
TMRxGE
/2
Q1
Synchronize
Synchronized
Interrupt
clock input
D
EN
det
det
Sleep input
Q
(3),(7)
To Comparator Module
DS41412D-page 161
Set
TMRxGIF
TXGCON
Data Bus
RD

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