PIC18F27J13-I/SP Microchip Technology, PIC18F27J13-I/SP Datasheet - Page 386

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PIC18F27J13-I/SP

Manufacturer Part Number
PIC18F27J13-I/SP
Description
IC PIC MCU 128KB FLASH 28SPDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18F27J13-I/SP

Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Controller Family/series
PIC18
Cpu Speed
48MHz
Digital Ic Case Style
DIP
Supply Voltage Range
1.8V To 5.5V
Embedded Interface Type
I2C, SPI, USART
Rohs Compliant
Yes
Core
PIC
Processor Series
PIC18F
Data Bus Width
8 bit
Maximum Clock Frequency
48 MHz
Data Ram Size
3.76 KB
On-chip Adc
Yes
Number Of Programmable I/os
2
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
A/d Bit Size
12 bit
A/d Channels Available
10
Height
3.43 mm
Interface Type
I2C, SPI, USART
Length
34.4 mm
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.15 V
Width
7.24 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180030 - BOARD DEMO PIC18F47J13 FS USBMA180029 - BOARD DEMO PIC18F47J53 FS USB
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
PIC18(L)F2X/4XK22
DAW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example1:
Example 2:
DS41412D-page 386
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
W
C
DC
W
C
DC
W
C
DC
W
C
DC
Q1
=
=
=
=
=
=
=
=
=
=
=
=
register W
Decimal Adjust W Register
DAW
None
If [W<3:0> > 9] or [DC = 1] then
(W<3:0>) + 6  W<3:0>;
else
(
If [W<7:4> + DC > 9] or [C = 1] then
(
else
(W<7:4>) + DC  W<7:4>
C
DAW adjusts the eight-bit value in W,
resulting from the earlier addition of two
variables (each in packed BCD format)
and produces a correct packed BCD
result.
1
1
DAW
W<3:0>)  W<3:0>;
W<7:4>) + 6 + DC  W<7:4>;
Read
0000
Q2
A5h
0
0
05h
1
0
CEh
0
0
34h
1
0
0000
Process
Data
Q3
0000
Write
Q4
W
0111
Preliminary
DECF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
CNT
Z
CNT
Z
Q1
=
=
=
=
register ‘f’
Decrement f
DECF f {,d {,a}}
0  f  255
d  [0,1]
a  [0,1]
(f) – 1  dest
C, DC, N, OV, Z
Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1
DECF
Read
0000
Q2
01h
0
00h
1
 2010 Microchip Technology Inc.
CNT,
01da
Process
Data
Q3
1, 0
ffff
for details.
destination
Write to
Q4
ffff

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