MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 225

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.7.4.5 Valid EOF and IFS Symbols
In
message occurs between A and B, the current symbol is considered a valid end-of-frame (EOF) symbol.
See
message occurs between C and D, the current symbol is considered a valid EOF symbol followed by a
valid inter-frame separation symbol (IFS). All nodes must wait until a valid IFS symbol time has expired
before beginning transmission. However, due to variations in clock frequencies and bus loading, some
nodes may recognize a valid IFS symbol before others and immediately begin transmitting. Therefore,
any time a node waiting to transmit detects a passive-to-active transition once a valid EOF has been
detected, it should immediately begin transmission, initiating the arbitration process.
15.7.4.6 Idle Bus
In
of the next message does not occur before D, the bus is considered to be idle, and any node wishing to
transmit a message may do so immediately.
Freescale Semiconductor
Figure
Figure
Figure
15-7(1), if the passive-to-active received transition beginning the SOF symbol of the next
15-7(2), if the passive-to-active received transition beginning the start-of-frame (SOF) symbol
15-7(2). If the passive-to-active received transition beginning the SOF symbol of the next
ACTIVE
PASSIVE
ACTIVE
PASSIVE
Figure 15-7. VPW Received Passive EOF and IFS Symbol Times
280 µs
M68HC12B Family Data Sheet, Rev. 9.1
300 µs
A
B
C
D
(1) VALID EOF SYMBOL
(2) VALID EOF+
IFS SYMBOL
BDLC MUX Interface
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