MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 270

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.12.8 msCAN12 Transmitter Control Register
ABTRQ2–ABTRQ0 — Abort Request Bits
TXEIE2–TXEIE0 — Transmitter Empty Interrupt Enable Bits
16.12.9 msCAN12 Identifier Acceptance Control Register
270
msCAN12 Controller
The CPU sets an ABTRQx bit to request that a scheduled message buffer (TXEx = 0) shall be aborted.
The msCAN12 grants the request if the message has not already started transmission, or if the
transmission is not successful (lost arbitration or error). When a message is aborted, the associated
TXE and the abort acknowledge flag (ABTAK) (see
are set and an TXE interrupt is generated if enabled. The CPU cannot reset ABTRQx. ABTRQx is
cleared implicitly whenever the associated TXE flag is set.
0 = No abort request
1 = Abort request pending
0 = No interrupt will be generated from this event.
1 = A transmitter empty (transmit buffer available for transmission) event will result in a transmitter
empty interrupt.
Address: $0107
Address: $0108
The software must not clear one or more of the TXE flags in CTFGL and
simultaneously set the respective ABTRQ bit(s).
The CTCR register is held in the reset state when the SFTRES bit in
CMCR0 is set.
Reset:
Reset:
Read:
Read:
Write:
Write:
Figure 16-23. msCAN12 Transmitter Control Register (CTCR)
Bit 7
Bit 7
0
0
0
0
Figure 16-24. msCAN12 Identifier Acceptance
= Unimplemented
= Unimplemented
ABTRQ2
6
0
6
0
0
M68HC12B Family Data Sheet, Rev. 9.1
Control Register (CIDAC)
ABTRQ1
IDAM1
5
0
5
0
NOTE
NOTE
ABTRQ0
IDAM0
4
0
4
0
16.12.7 msCAN12 Transmitter Flag
3
0
0
3
0
0
TXEIE2
IDHIT2
2
0
2
0
TXEIE1
IDHIT1
1
0
1
0
Freescale Semiconductor
TXEIE0
IDHIT0
Bit 0
Bit 0
0
0
Register)