MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 275

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AM7–AM0 — Acceptance Mask Bits
16.12.14 msCAN12 Port CAN Control Register
These bits control pins 7–2 of port CAN control register. Pins 1 and 0 are reserved for the RxCAN (input
only) and TxCAN (output only) pins.
PUECAN — Pullup Enable Port CAN Bit
RDPCAN — Reduced Drive Port CAN
16.12.15 msCAN12 Port CAN Data Register
PCAN7–PCAN2 — Port CAN Data Bits
Freescale Semiconductor
If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier
acceptance register must be the same as its identifier bit before a match will be detected. The message
will be accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit
in the identifier acceptance register will not affect whether or not the message is accepted.
Writing to PCANx stores the bit value in an internal bit memory. This value is driven to the respective
pin only if DDRCANx = 1.
Reading PCANx returns:
Reading bits 1 and 0 returns the value of the TxCAN and RxCAN pins, respectively.
1 = Ignore corresponding acceptance code register bit.
0 = Match corresponding acceptance code register and identifier bits.
0 = Pull mode disabled for port CAN
1 = Pull mode enabled for port CAN
0 = Reduced drive disabled for port CAN
1 = Reduced drive enabled for port CAN
• Value of the internal bit memory driven to the pin, if DDRCANx = 1
• Value of the respective pin, if DDRCANx = 0
Address: $013D
Address: $013E
The CIDMR0–CIDMR7 registers can be written only if the SFTRES bit in
CMCR0 is set.
Reset:
Reset:
Read:
Read:
Write:
Write:
Figure 16-31. msCAN12 Port CAN Control Register (PCTLCAN)
Figure 16-32. msCAN12 Port CAN Data Register (PORTCAN)
PCAN7
Bit 7
Bit 7
0
0
= Unimplemented
= Unimplemented
PCAN6
6
0
0
6
M68HC12B Family Data Sheet, Rev. 9.1
PCAN5
5
0
0
5
NOTE
PCAN4
Unaffected by reset
4
0
0
4
PCAN2
3
0
0
3
Programmer’s Model of Control Registers
PCAN2
2
0
0
2
PUECAN
TxCAN
1
0
1
RDPCAN
RxCAN
Bit 0
Bit 0
0
275