MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 240

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Byte Data Link Communications (BDLC)
15.9.5 BDLC Analog Roundtrip Delay Register
Read: Anytime
Write: Once in normal modes or anytime in special mode
BARD programs the BDLC to compensate for various delays of external transceivers.
ATE — Analog Transceiver Enable Bit
RXPOL — Receive Pin Polarity Bit
BO3–BO0 — BARD Offset Bits
240
The ATE bit is used to select either the on-board or an off-chip analog transceiver.
This bit selects the polarity of an incoming signal on the receive pin. Some external analog transceivers
invert the receive signal from the J1850 bus before feeding it back to the digital receive pin.
These bits are used to compensate for the analog transceiver roundtrip delay.
expected transceiver delay with respect to BARD offset values.
0 = Select off-chip analog transceiver.
1 = Select on-board analog transceiver.
0 = Select inverted polarity, where external transceiver inverts the receive signal.
1 = Select normal/true polarity; true non-inverted signal from J1850 bus, for example, the external
transceiver does not invert the receive signal.
Address:
This device does not contain an on-board transceiver; ATE should be
cleared for proper operation.
Reset:
Read:
Write:
Figure 15-17. BDLC Analog Roundtrip Delay Register (BARD)
$00FC
Bit 7
ATE
1
= Unimplemented
RXPOL
M68HC12B Family Data Sheet, Rev. 9.1
6
1
5
0
0
NOTE
4
0
0
BO3
3
0
BO2
2
1
BO1
1
1
Table 15-5
Freescale Semiconductor
Bit 0
BO0
1
shows the