MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 245

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.3.2 Receive Structures
The received messages are stored in a 2-stage first-in/first-out (FIFO) input. The two message buffers are
mapped into a single memory area (see
exclusively associated to the msCAN12, the foreground receive buffer (RxFG) is addressable by the
CPU12. This scheme simplifies the handler software since only one address area is applicable for the
receive process.
Both buffers have 13 bytes for storing the CAN control bits, the identifier (standard or extended), and the
data contents. For details, see
The receiver full flag (RXF) in the msCAN12 receiver flag register (CRFLG) signals the status of the
foreground receive buffer. When the buffer contains a correctly received message with matching
identifier, this flag is set. See
On reception, each message is checked to see if it passes the filter (for details see
Acceptance
RxFG
to read the received message from RxFG and then reset the RXF flag to acknowledge the interrupt and
Freescale Semiconductor
(1)
, sets the RXF flag, and emits a receive interrupt to the CPU
Filter) and in parallel is written into RxBG. The msCAN12 copies the content of RxBG into
Figure 16-2. User Model for Message Buffer Organization
msCAN12
16.12.5 msCAN12 Receiver Flag
16.11 Programmer’s Model of Message
M68HC12B Family Data Sheet, Rev. 9.1
Figure
RxBG
Tx0
RxFG
Tx1
Tx2
16-2). While the background receive buffer (RxBG) is
PRIO
PRIO
PRIO
RXF
TXE
TXE
TXE
Register.
CPU BUS
(2)
. The user’s receive handler has
Storage.
16.4 Identifier
Message Storage
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