MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 30

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

General Description
1.6.3.8 ADDR15–ADDR0 and DATA15–DATA0
ADDR15–ADDR0 and DATA15–DATA0 are the external address and data bus pins. They share functions
with general-purpose I/O ports A and B. In single-chip operating modes, the pins can be used for I/O; in
expanded modes, the pins are used for the external buses.
In expanded wide mode, ports A and B multiplex 16-bit data and address buses. The PA7–PA0 pins
multiplex ADDR15–ADDR8 and DATA15–DATA8. The PB7–PB0 pins multiplex ADDR7–ADDR0 and
DATA7–DATA0.
In expanded narrow mode, ports A and B are used for the 16-bit address bus. An 8-bit data bus is
multiplexed with the most significant half of the address bus on port A. In this mode, 16-bit data is handled
as two back-to-back bus cycles, one for the high byte followed by one for the low byte. The PA7–PA0 pins
multiplex ADDR15–ADDR8, DATA15–DATA8, and DATA7–DATA0. The state of the address pin should
be latched at the rising edge of E. To allow for maximum address setup time at external devices, a
transparent latch should be used.
1.6.3.9 R/W
R/W is the read/write pin. In all modes, this pin can be used as input/output (I/O) and is a general-purpose
input with an active pullup out of reset. If the read/write function is required, it should be enabled by setting
the RDWE bit in the port E assignment register (PEAR). External writes are not possible until enabled.
1.6.3.10 LSTRB
LSTRB is the low-byte strobe pin. In all modes, this pin can be used as I/O and is a general-purpose input
with an active pullup out of reset. If the strobe function is required, it should be enabled by setting the
LSTRE bit in the PEAR register. This signal is used in write operations and so external low-byte writes
are not possible until this function is enabled. This pin is also used as TAGLO in special expanded modes
and is multiplexed with the LSTRB function.
1.6.3.11 IPIPE1 and IPIPE0
IPIPE1 and IPIPE0 are the instruction queue tracking pins. Their signals are used to track the state of the
internal instruction execution queue. Execution state is time-multiplexed on the two signals.
1.6.3.12 DBE
DBE is the data bus enable signal. It is an active-low signal that is asserted low during E-clock high time.
DBE provides separation between output of a multiplexed address and the input of data. When an
external address is stretched, DBE is asserted during what would be the last quarter cycle of the last
E-clock cycle of stretch. In expanded modes, this pin is used to enable the drive control of external buses
during external reads only. Use of the DBE is controlled by the NDBE bit in the PEAR register. DBE is
enabled out of reset in expanded modes. This pin has an active pullup during and after reset in single-chip
modes.
M68HC12B Family Data Sheet, Rev. 9.1
30
Freescale Semiconductor