MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 242

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Byte Data Link Communications (BDLC)
15.9.7 Port DLC Data Register
Read: Anytime
Write: Anytime
This register holds data to be driven out on port DLC pins or data received from port DLC pins.
When configured as an input, a read returns the pin level. When configured as output, a read returns the
latched output data.
Writes do not change pin state when the pins are configured for BDLC output. Upon reset, pins are
configured for general-purpose high impedance inputs.
15.9.8 Port DLC Data Direction Register
Read: Anytime
Write: Anytime
DDDLC6–DDDLC0 — Data Direction Port DLC Bits
242
1 = Configure I/O pin for output
0 = Configure I/O pin for input only
Alternate Pin Function:
Address: $00FE
Address:
Reset:
Read:
Write:
Figure 15-20. Port DLC Data Direction Register (DDRDLC)
Reset:
Read:
Write:
Bit 7
$00FF
Figure 15-19. Port DLC Data Register (PORTDLC)
0
0
Bit 7
0
0
= Unimplemented
DDDLC6
6
0
M68HC12B Family Data Sheet, Rev. 9.1
= Unimplemented
Bit 6
U
6
DDDLC5
5
0
Bit 5
U
5
DDDLC4
4
0
U = Unaffected
Bit 4
U
4
DDDLC3
3
0
Bit 3
U
3
DDDLC2
2
0
Bit 2
U
2
DDDLC1
1
0
DLCTX
Freescale Semiconductor
Bit 1
U
1
DDDLC0
Bit 0
0
DLCRX
Bit 0
Bit 0
U