HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 133
![IC SUPERH MCU FLASH 256K 112QFP](/photos/12/21/122194/hd64f7144f50v_sml.jpg)
HD64F7144F50V
Manufacturer Part Number
HD64F7144F50V
Description
IC SUPERH MCU FLASH 256K 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Specifications of HD64F7144F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F7144F50V
Manufacturer:
RENESAS
Quantity:
450
Company:
Part Number:
HD64F7144F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F7144F50V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Table 5.17 DSP Operation Instruction Categories
Classification
ALU
arithmetic
operation
instructions
ALU logical operation instructions
Fixed decimal point multiplication
instruction
Shift
System control instructions
ALU fixed decimal
point operation
instructions
ALU integer operation
instructions
MSB detection
instruction
Rounding operation
instruction
Arithmetic shift
operation instruction
Logical shift operation
instruction
Instruction
Types
11
2
1
1
3
1
1
1
2
Total 23
Operation
Code
PABS
PADD
PADD
PMULS
PADDC
PCLR
PCMP
PCOPY
PNEG
PSUB
PSUB
PMULS
PSUBC
PDEC
PINC
PDMSB
PRND
PAND
POR
PXOR
PMULS
PSHA
PSHL
PLDS
PSTS
Rev. 5.00 Jun 30, 2004 page 117 of 512
Function
Absolute value operation
Addition
Addition and signed
multiplication
Clear
Compare
Copy
Invert sign
Subtraction
Subtraction and signed
multiplication
Subtraction with borrow
Logical AND
Logical OR
Logical exclusive OR
Signed multiplication
Logical shift
Store from system register
Addition with carry
Decrement
Increment
MSB detection
Rounding
Arithmetic shift
System register load
Section 5 Instruction Set
REJ09B0171-0500O
No. of
Instructions
28
12
6
2
9
1
4
4
12
Total 78
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