HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 406

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Instruction Descriptions
6.3.20
Format
PSUB Sx,Sy,Dz
DCT PSUB
Sx,Sy,Dz
DCF PSUB
Sx,Sy,Dz
Description: Subtracts the contents of the Sy operand from the Sx operand and stores the result in
the Dz operand. When conditions are specified for DCT and DCF, the instruction is executed
when those conditions are TRUE. When they are FALSE, the instruction is not executed.
When conditions are not specified, the DC bit of the DSR register is updated according to the
specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are updated. If
conditions are specified, the DC, N, Z, V, and GT bits are not updated even is the conditions were
true and the instruction was executed.
Rev. 5.00 Jun 30, 2004 page 390 of 512
REJ09B0171-0500O
[if cc]PSUB (Subtract with Condition): DSP Arithmetic Operation Instruction
Abstract
Sx – Sy Dz
if DC 1,
Sx – Sy Dz if 0, nop
if DC 0,
Sx – Sy Dz if 1, nop
111110**********
10100001xxyyzzzz
111110**********
10100010xxyyzzzz
111110**********
10100011xxyyzzzz
Code
Cycle
1
1
1
Update
—
—
DC Bit
SH-1
—
—
—
Instructions
Applicable
SH-2
—
—
—
SH-
DSP