HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 99

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.18
The SH-DSP repeat (loop) control function is a special utility for controlling repetition efficiently.
The SETRC instruction is executed to hold a repeat count in the repeat counter (RC, 12 bits) and
set an execution mode in which the repeat (loop) program is repeated until the RC is 1. Upon
completion of the repeat operation, the content of the RC becomes 0.
The repeat start register (RS) holds the start address of the repeated section. The repeat end
register (RE) holds the ending address of the repeated section. (There are some exceptions. See
4.19.1 Notes.) The repeat counter (RC) holds the repeat count. The procedure for executing repeat
control is shown below:
1. Set the repeat start address in the RS register.
2. Set the repeat end address in the RE register.
3. Set the repeat count in the RC counter.
4. Execute the repeated program (loop).
The following instructions are used for executing 1 and 2:
The SETRC instruction is used to execute 3 and 4. Immediate data or a general register may be
used to specify the repeat count as the operand of the SETRC instruction:
#imm is 8 bits and the RC counter is 12 bits, so to set the RC counter to a value of 256 or greater,
use the Rm register. A sample program is shown below.
LDRS @(disp,PC);
LDRE @(disp,PC);
SETRC #imm;
SETRC Rm;
; instr1~5 executes repeatedly
RptStart: instrl;
DSP Repeat (Loop) Control
LDRS
LDRE
SETRC #imm;
instr0;
instr2;
instr3;
instr4;
#imm
Rm
RptStart;
RptEnd;
Rc, enable repeat control
Rc, enable repeat control
RC=#imm
Rev. 5.00 Jun 30, 2004 page 83 of 512
Section 4 Instruction Features
REJ09B0171-0500O