HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 43
![IC SUPERH MCU FLASH 256K 112QFP](/photos/12/21/122194/hd64f7144f50v_sml.jpg)
HD64F7144F50V
Manufacturer Part Number
HD64F7144F50V
Description
IC SUPERH MCU FLASH 256K 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Specifications of HD64F7144F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F7144F50V
Manufacturer:
RENESAS
Quantity:
450
Company:
Part Number:
HD64F7144F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F7144F50V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Table 4.4
Note: The address of the immediate data is accessed by @(disp, PC).
Absolute Address: When data is accessed by absolute address, the value already in the absolute
address is placed in the memory table. Loading the immediate data when the instruction is
executed transfers that value to the register and the data is accessed in the indirect register
addressing mode.
Table 4.5
16-Bit/32-Bit Displacement: When data is accessed by 16-bit or 32-bit displacement, the pre-
existing displacement value is placed in the memory table. Loading the immediate data when the
instruction is executed transfers that value to the register and the data is accessed in the indirect
indexed register addressing mode.
Table 4.6
Classification
8-bit immediate
16-bit immediate
32-bit immediate
Classification
Absolute address
Classification
16-bit displacement
Immediate Data Accessing
Absolute Address
Displacement Accessing
SH-1/SH-2/SH-DSP CPU
MOV
MOV.W
.DATA.W
MOV.L
.DATA.L
SH-1/SH-2/SH-DSP CPU
MOV.L
MOV.B
.DATA.L
SH-1/SH-2/SH-DSP CPU
MOV.W
MOV.W
.DATA.W
.................
.................
..................
..................
#H'12,R0
@(disp,PC),R0
H'1234
@(disp,PC),R0
H'12345678
@(disp,PC),R1
@R1,R0
H'12345678
@(disp,PC),R0
@(R0,R1),R2
H'1234
Rev. 5.00 Jun 30, 2004 page 27 of 512
Example for Other CPU
MOV.B
Example for Other CPU
MOV.B
MOV.W
MOV.L
Example for Other CPU
MOV.W
Section 4 Instruction Features
#H'12,R0
#H'1234,R0
#H'12345678,R0
@H'12345678,R0
@(H'1234,R1),R2
REJ09B0171-0500O
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