HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 90

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 4 Instruction Features
4.13.4
The condition bits are set as follows. They are updated as for ALU fixed decimal point arithmetic
operations.
4.13.5
When the S bit of the SR register is set to 1, the overflow prevention function can be specified for
all rounding processing executed by the DSP unit. When the operation result overflows, the
maximum (positive) or minimum (negative) value is stored.
4.14
DSP instructions may be either conditional or unconditional. Unconditional instructions are
executed without regard to the DSP condition bit (DC bit), but conditional instructions may
reference the DC bit before they are executed. With unconditional instructions, the DSR register’s
DC bit and condition bits (N, Z, V, and GT) are updated according to the results of the ALU
operation or shift operation. The DC bit and condition bits (N, Z, V, and GT) are not updated
regardless of whether the conditional instruction is executed. The DC bit is updated according to
the specifications of the condition select (CS) bits. Updates differ for arithmetic operations, logical
operations, arithmetic shifts and logical shifts. Table 4.28 shows the relationship between the CS
bits and the DC bit.
Rev. 5.00 Jun 30, 2004 page 74 of 512
REJ09B0171-0500O
The N bit is the same as the result of the ALU fixed decimal point arithmetic operation. It is set
to 1 for a negative operation result and 0 for a positive operation result.
The Z bit is the same as the result of the ALU fixed decimal point arithmetic operation. It is set
to 1 when the operation result is zero; otherwise, the Z bit is 0.
The V bit is the same as the result of the ALU fixed decimal point arithmetic operation. It is set
to 1 for an overflow; otherwise, the V bit is 0.
The GT bit is the same as the result of the ALU fixed decimal point arithmetic operation and
the ALU integer operation. It is set 1 for a positive operation result; otherwise, the GT bit is 0.
Condition Bits
Overflow Prevention Function (Saturation Operation)
Condition Select Bits (CS) and the DSP Condition Bit (DC)