HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 330

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Instruction Descriptions
6.3.4
Format
PADDC Sx,
Sy, Dz
Description: Adds the contents of the Sx and Sy operands to the DC bit and stores the result in the
Dz operand. The DC bit of the DSR register is updated as the carry flag. The N, Z, V, and GT bits
of the DSR register are also updated.
Note: The DC bit is updated as the carry flag after execution of the PADDC instruction
Operation:
Rev. 5.00 Jun 30, 2004 page 314 of 512
REJ09B0171-0500O
/* PADD Sx,Sy,Dz
{
unsigned char carry_bit, negative_bit, zero_bit, overflow_bit;
/* ALU Sources assignment */
switch (xx) {
case 0x0: DSP_ALU_SRC1
case 0x1: DSP_ALU_SRC1
case 0x2: DSP_ALU_SRC1
case 0x3: DSP_ALU_SRC1
regardless of the CS bits.
PADDC (Addition with Carry): DSP Arithmetic Operation Instruction
Abstract
Sx + Sy + DC
if (DSP_ALU_SRC1_MSB) DSP_ALU_SRC1G = 0xff;
else
break;
if (DSP_ALU_SRC1_MSB) DSP_ALU_SRC1G = 0xff;
else
break;
DSP_ALU_SRC1G = A0G;
break;
DSP_ALU_SRC1G = A1G;
break;
/* Sx Operand selection bit (xx) */
*/
Dz
Code
111110**********
10110000xxyyzzzz
DSP_ALU_SRC1G = 0x0;
DSP_ALU_SRC1G = 0x0;
= X0;
= X1;
= A0;
= A1;
Cycle DC Bit SH-1 SH-2
1
Carry
—
Instructions
Applicable
—
SH-
DSP