HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 146

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Instruction Descriptions
Rev. 5.00 Jun 30, 2004 page 130 of 512
REJ09B0171-0500O
2. 16-bit instruction code that is not assigned as instructions is handled as an ordinary
3. An ordinary illegal instruction or branched instruction (i.e., an illegal slot instruction)
4. The delayed branch actual occurs after the slot instruction is executed. Except for
5. When there ia an ordinary illegal instruction, branched instruction or an instruction to
@(disp:8, PC); Indirect PC addressing with displacement
disp:8, disp:12:; PC relative addressing
illegal instruction and produces illegal instruction exception processing.
Example: H'FFFF [ordinary illegal instruction]
that follows a BRA, BT/S or another delayed branch instruction will cause illegal
instruction exception processing.
Example 1:
....
BRA
.data.w H'FFFF
....
Example 2:
RTE
BT/S
branches such as register updates, however, delayed branch instructions are executed
before delayed slot instructions. For example, even when the contents of a register that
stores a branch destination address in a delay slot are changed, the branch destination
remains the register contents prior to the change.
renew the SR, RS or RE register (SETRC, LDRS, etc.) in the last three instructions of a
repeat program (loop) with three or less instructions or a program (loop) with four or
more instructions, illegal instruction exception processing is started. Refer to section
4.18, DSP Repeat (Loop) Control, for more information.
LABEL
LABEL
[H'FFFF is an ordinary illegal instruction from the start]
Illegal slot instruction
Illegal slot instruction