HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 451

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Notes: 1. The normal minimum number of execution cycles. (The number in parentheses is the
Type
System
control
instructions
(cont)
2. One state when there is no branch.
3. Number of stages of the SH-1 CPU.
number of cycles when there is contention with following instructions.
Category
MAC
register
transfer
instruction
DSP
register
transfer
instruction
MAC
memory
transfer
instruction
DSP
memory
transfer
instruction
RTE
instruction
TRAP
instruction
SLEEP
instruction
Instruction
STS
STS
STS
STS
STS
STS
STS
STS
STS.L
STS.L
STS.L
STS.L
STS.L
STS.L
STS.L
STS.L
RTE
TRAPA
SLEEP
MACH,Rn
MACL,Rn
DSR,Rn
A0,Rn
X0,Rn
X1,Rn
Y0,Rn
Y1,Rn
MACH,@–Rn
MACL,@–Rn
DSR,@–Rn
A0,@–Rn
X0,@–Rn
X1,@–Rn
Y0,@–Rn
Y1,@–Rn
#imm
Rev. 5.00 Jun 30, 2004 page 435 of 512
5
4
4
5
9
3
Stages
Section 7 Pipeline Operation
Cycles
1
1
1
4
8
3
REJ09B0171-0500O
Contention
• Contention
• Contention
• MA contends
• Contention
• MA contends
—
—
—
—
occurs with
multiplier
occurs when an
instruction that
uses the same
destination
register is
placed
immediately
after this
instruction
with IF
occurs with
multiplier
with IF