HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 37
![IC SUPERH MCU FLASH 256K 112QFP](/photos/12/21/122194/hd64f7144f50v_sml.jpg)
HD64F7144F50V
Manufacturer Part Number
HD64F7144F50V
Description
IC SUPERH MCU FLASH 256K 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Specifications of HD64F7144F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F7144F50V
Manufacturer:
RENESAS
Quantity:
450
Company:
Part Number:
HD64F7144F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F7144F50V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Section 3 Data Formats
In single data transfers, the A0G and A1G registers can be handled as independent registers. Eight
bits of data can be loaded to or stored from the A0G and A1G registers.
When the A0G or A1G register is the source register, only eight bits are stored from the register.
The top bits are sign extended.
When the A0G or A1G register is the destination register, the bottom eight bits are loaded to the
register. The A0 and A1 registers are not cleared with zeros, so the values are preserved.
Tables 3.1 and 3.2 list the data formats on the register with the DSP instructions. With some
instructions, not all registers can be accessed. For example, the PMULS instruction can specified
the A1 register as the source register, but not the A0 register. For more information, see the
description of the instruction.
Figure 3.5 shows the relationship between the DSP registers and buses during data transfers.
Rev. 5.00 Jun 30, 2004 page 21 of 512
REJ09B0171-0500O
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