HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 87
![IC SUPERH MCU FLASH 256K 112QFP](/photos/12/21/122194/hd64f7144f50v_sml.jpg)
HD64F7144F50V
Manufacturer Part Number
HD64F7144F50V
Description
IC SUPERH MCU FLASH 256K 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Specifications of HD64F7144F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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HD64F7144F50V
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4.12.4
The condition bits are set as follows.
4.13
4.13.1
The DSP unit has a function for rounding 32-bit values to 16-bit values. When the value has guard
bits, 40 bits are rounded to 24 bits. When the rounding instruction is executed, H'0000 8000 is
added to the source operand and the bottom word is then cleared to zeros.
Rounding uses all bits of the source and destination operands. The action of the operation is the
same as for fixed decimal point operations and is executed in the DSP stage (the last stage) of the
pipeline.
The rounding instruction is unconditional. The DSR register’s DC, N, Z, V, and GT bits are thus
always updated according to the operation result.
Figure 4.17 shows the rounding flowchart. Figure 4.18 shows the rounding process definitions.
The N bit is the same as the result of the ALU integer operation. It is set to 1 for a negative
operation result and 0 for a positive operation result.
The Z bit is the same as the result of the ALU integer operation. It is set to 1 when the
operation result is zero; otherwise, the Z bit is 0.
The V bit is always 0.
The GT bit is the same as the result of the ALU integer operation. It is set 1 for a positive
operation result and otherwise to 0.
Operation Function
Condition Bits
Rounding
Rev. 5.00 Jun 30, 2004 page 71 of 512
Section 4 Instruction Features
REJ09B0171-0500O
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