HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 519

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Instruction
DT
EXTS.B
EXTS.W
EXTU.B
EXTU.W
JMP
JSR
LDC
LDC
LDC
LDC
LDC
LDC
LDC.L
LDC.L
LDC.L
LDC.L
LDC.L
LDC.L
LDRE
LDRS
LDS
LDS
LDS
LDS
LDS
Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
@Rm
@Rm
Rm,GBR
Rm,MOD
Rm,RE
Rm,RS
Rm,SR
Rm,VBR
@Rm+,GBR
@Rm+,MOD
@Rm+,RE
@Rm+,RS
@Rm+,SR
@Rm+,VBR
@(disp,PC) disp
@(disp,PC) disp
Rm,A0
Rm,DSR
Rm,MACH
Rm,MACL
Rm,PR
Rm
Operation
Rn – 1
1
0
A byte in Rm is sign-
extended
A word in Rm is sign-
extended
A byte in Rm is zero-
extended
A word in Rm is zero-
extended
Delayed branch,
Rm
Delayed branch,
PC
Rm
Rm MOD
Rm RE
Rm RS
Rm SR
Rm VBR
(Rm) GBR,Rm+4 Rm
(Rm) MOD,Rn+4 Rn
(Rm) RE,Rn+4 Rn
(Rm) RS,Rn+4 Rn
(Rm) SR,Rm+4 Rm
(Rm) VBR,Rm+4 Rm
Rm
Rm
Rm
Rm
T. When Rn is nonzero,
T
PR, Rm
2 +PC RE
2 +PC RS
PC
GBR
A0
DSR
MACH
MACL
PR
Rn, when Rn is 0,
Rn
Rn
Rn
Rn
PC
Code
0100nnnn00010000
0110nnnnmmmm1110
0110nnnnmmmm1111
0110nnnnmmmm1100
0110nnnnmmmm1101
0100mmmm00101011
0100mmmm00001011
0100mmmm00011110
0100mmmm01011110
0100mmmm01111110
0100mmmm01101110
0100mmmm00001110
0100mmmm00101110
0100mmmm00010111
0100mmmm01010111
0100mmmm01110111
0100mmmm01100111
0100mmmm00000111
0100mmmm00100111
10001110dddddddd
10001100dddddddd
0100mmmm01111010
0100mmmm01101010
0100mmmm00001010
0100mmmm00011010
0100mmmm00101010
Rev. 5.00 Jun 30, 2004 page 503 of 512
Appendix A CPU Instructions
REJ09B0171-0500O
Cycles T Bit
1
1
1
1
1
2
2
1
1
1
1
1
1
3
3
3
3
3
3
1
1
1
1
1
1
1
—
—
—
—
—
—
Comp-
arison
result
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—
—
—
—
—
—
—
LSB
—
—
—
—
—
LSB
—
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