LPC3230FET296,551 NXP Semiconductors, LPC3230FET296,551 Datasheet
LPC3230FET296,551
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LPC3230FET296,551 Summary of contents
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LPC3220/30/40/50 16/32-bit ARM microcontrollers; hardware floating-point coprocessor, USB On-The-Go, and EMC memory interface Rev. 01.03 — 16 March 2010 1. General description The LPC3220/30/40/50 embedded microcontrollers were designed for low power, high performance applications. NXP achieved their performance goals using ...
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... NXP Semiconductors Multi-layer AHB system that provides a separate bus for each AHB master, including both an instruction and data bus for the CPU, two data busses for the DMA controller, and another bus for the USB controller, one for the LCD, and a final one for the Ethernet MAC ...
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... NXP Semiconductors Six enhanced timer/counters which are architecturally identical except for the peripheral base address. Two capture inputs and two match outputs are pinned out to four timers. Timer 1 brings out a third match output, timers 2 and 3 bring out all four match outputs, timer 4 has one match output, and timer 5 has no inputs or outputs ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information [1] Type number Package Name [2] LPC3220FET296 TFBGA296 [2] LPC3230FET296 TFBGA296 [2] LPC3240FET296 TFBGA296 [2] LPC3250FET296 TFBGA296 [3] LPC3220FET296/01 TFBGA296 [3] LPC3230FET296/01 TFBGA296 [3] LPC3240FET296/01 TFBGA296 [3] LPC3250FET296/01 TFBGA296 F = −40 °C to +85 °C temperature range. Note that Revision “A” parts with and without the /01 suffix are identical. For example, [1] LPC3220FET296 Revision “ ...
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... NXP Semiconductors 5. Block diagram ETB ETM 9 VFP9 ARM D-CACHE I-CACHE 9EJS D-SIDE I-SIDE MMU CONTROLLER CONTROLLER DATA INSTRUCTION master layer 0 1 slave port 32-bit AHB matrix = Master/Slave connection supported by the multilayer AHB matrix Fig 1. Block diagram of LPC3220/30/40/50 LPC3220_30_40_50_1 Product data sheet ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Pin configuration for SOT1048-1 (TFBGA296) Table 3. Pin allocation table (TFBGA296) Pin Symbol Row A A4 I2S1TX_CLK/MAT3[0] A7 MS_DIO1/MAT0[1] A10 SPI2_DATIN/MISO1/ [1] LCDVD[21] /GPI_27 [1] A13 GPO_21/U4_TX/LCDVD[3] [1] A16 GPO_6/LCDVD[18] Row B B4 I2S1TX_WS/CAP3[0] B7 MS_SCLK/MAT2[0] [1] B10 SPI2_CLK/SCK1/LCDVD[23] [1] B13 GPO_13/MCOB1/LCDDCLK B16 GPI_8/KEY_COL6/ ...
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... NXP Semiconductors Table 3. Pin allocation table (TFBGA296) Pin Symbol C10 SPI1_DATIN/MISO0/GPI_25/ MCI1 [1] C13 GPO_8/LCDVD[8] C16 GPI_0/I2S1RX_SDA Row D D1 FLASH_RDY D4 GPO_1 D7 P0[1]/I2S1RX_WS [1] D10 GPO_16/MCOB0/LCDENAB / [1] LCDM D13 GPI_7/CAP4[0]/MCABORT [2] D16 KEY_ROW3/ENET_TX_EN Row E E1 FLASH_IO[3] E4 I2C2_SDA E7 I2S1TX_SDA/MAT3[1] E10 GPO_22/U7_HRTS/ [1] LCDVD[14] E13 GPI_4/SPI1_BUSY [2] E16 KEY_COL1/ENET_RX_CLK ...
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... NXP Semiconductors Table 3. Pin allocation table (TFBGA296) Pin Symbol [1] H16 HIGHCORE/LCDVD[17] Row J J1 EMC_A[20]/P1[20] J4 EMC_A[23]/P1[23] J7 VDD_CORE J13 VDD_IOA J16 JTAG_TDI Row K K1 EMC_A[19]/P1[19] K4 EMC_A[17]/P1[17] K7 VDD_EMC K13 VSS_IOA K16 U1_TX Row L L1 EMC_A[15]/P1[15] L4 EMC_A[1]/P1[1] L7 VSS_CORE L13 VDD_RTCCORE ...
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... NXP Semiconductors Table 3. Pin allocation table (TFBGA296) Pin Symbol P7 VSS_EMC P10 VSS_EMC P13 VSS_AD P16 RTCX_IN Row R R1 EMC_A[13]/P1[13] R4 EMC_WR R7 EMC_D[1] R10 EMC_D[24]/P2[5] R13 TS_XP R16 VSS_PLLUSB Row T T1 EMC_DQM[2] T4 EMC_CLKIN T7 EMC_D[11] T10 EMC_D[23]/P2[4] T13 EMC_BLS[1] T16 VDD_PLL397 ...
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... NXP Semiconductors 6.2 Pin description Table 4. Pin description Symbol Pin Power supply domain ADIN0/TS_YM U15 VDD_AD ADIN1/TS_XM T14 VDD_AD ADIN2/TS_AUX_IN V16 VDD_AD DBGEN G14 VDD_IOD EMC_A[0]/P1[0] L3 VDD_EMC EMC_A[1]/P1[1] L4 VDD_EMC EMC_A[2]/P1[2] M1 VDD_EMC EMC_A[3]/P1[3] M2 VDD_EMC EMC_A[4]/P1[4] M3 VDD_EMC EMC_A[5]/P1[5] ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Power supply domain EMC_A[15]/P1[15] L1 VDD_EMC EMC_A[16]/P1[16] K3 VDD_EMC EMC_A[17]/P1[17] K4 VDD_EMC EMC_A[18]/P1[18] K2 VDD_EMC EMC_A[19]/P1[19] K1 VDD_EMC EMC_A[20]/P1[20] J1 VDD_EMC EMC_A[21]/P1[21] J2 VDD_EMC EMC_A[22]/P1[22] J3 VDD_EMC EMC_A[23]/P1[23] J4 VDD_EMC EMC_BLS[0] U14 VDD_EMC ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Power supply domain EMC_D[9] U6 VDD_EMC EMC_D[10] V6 VDD_EMC EMC_D[11] T7 VDD_EMC EMC_D[12] U7 VDD_EMC EMC_D[13] V7 VDD_EMC EMC_D[14] T8 VDD_EMC EMC_D[15] U8 VDD_EMC EMC_D[16]/ V8 VDD_EMC EMC_DQS0 EMC_D[17]/ R9 VDD_EMC EMC_DQS1 EMC_D[18]/ V9 VDD_EMC EMC_CLK EMC_D[19]/P2[0] U9 VDD_EMC EMC_D[20]/P2[1] T9 VDD_EMC EMC_D[21]/P2[2] ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Power supply domain EMC_DQM[1] P4 VDD_EMC EMC_DQM[2] T1 VDD_EMC EMC_DQM[3] P5 VDD_EMC EMC_DYCS0 R6 VDD_EMC EMC_DYCS1 G1 VDD_EMC EMC_OE H1 VDD_EMC EMC_RAS T2 VDD_EMC EMC_WR R4 VDD_EMC FLASH_ALE D2 VDD_IOC FLASH_CE E3 VDD_IOC FLASH_CLE F3 VDD_IOC FLASH_IO[0] H2 VDD_IOC FLASH_IO[1] H3 VDD_IOC FLASH_IO[2] F1 VDD_IOC FLASH_IO[3] E1 VDD_IOC ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Power supply domain GPI_7/CAP4[0]/ D13 VDD_IOD MCABORT GPI_8/KEY_COL6/ B16 VDD_IOD SPI2_BUSY/ ENET_RX_DV GPI_9/KEY_COL7/ E12 VDD_IOD ENET_COL GPI_19/U4_RX B15 VDD_IOD GPI_28/U3_RI N17 VDD_IOA GPIO_0 A12 VDD_IOD GPIO_1 A11 VDD_IOD GPIO_2/ D9 VDD_IOD KEY_ROW6/ ENET_MDC GPIO_3/ ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Power supply domain GPO_5 B3 VDD_IOC GPO_6/ A16 VDD_IOD LCDVD[18] GPO_7/ A15 VDD_IOD LCDVD[2] GPO_8/ C13 VDD_IOD LCDVD[8] GPO_9/ C12 VDD_IOD LCDVD[9] GPO_10/ E11 VDD_IOD MCOB2/ LCDPWR GPO_11 E8 VDD_IOB GPO_12/ B12 VDD_IOD MCOA2/ LCDLE ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Power supply domain GPO_22/ E10 VDD_IOD U7_HRTS/ LCDVD[14] GPO_23/ M16 VDD_IOA U2_HRTS/ U3_RTS HIGHCORE/ H16 VDD_IOD LCDVD[17] I2C1_SCL A5 VDD_IOB I2C1_SDA B6 VDD_IOB I2C2_SCL A3 VDD_IOC I2C2_SDA E4 VDD_IOC I2S1TX_CLK/ A4 VDD_IOB MAT3[0] I2S1TX_SDA/ E7 VDD_IOB MAT3[1] I2S1TX_WS/ B4 VDD_IOB ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Power supply domain KEY_COL5/ F16 VDD_IOD ENET_RXD1 KEY_ROW0/ E15 VDD_IOD ENET_TX_ER KEY_ROW1/ E14 VDD_IOD ENET_TXD2 KEY_ROW2/ F14 VDD_IOD ENET_TXD3 KEY_ROW3/ D16 VDD_IOD ENET_TX_EN KEY_ROW4/ C17 VDD_IOD ENET_TXD0 KEY_ROW5/ C18 VDD_IOD ENET_TXD1 MS_BS/MAT2[1] A6 VDD_IOD ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Power supply domain P0[2]/ M17 VDD_IOA I2S0RX_SDA/ LCDVD[4] P0[3]/ M18 VDD_IOA I2S0RX_CLK/ LCDVD[5] P0[4]/ L15 VDD_IOA I2S0RX_WS/ LCDVD[6] P0[5]/ L16 VDD_IOA I2S0TX_SDA/ LCDVD[7] P0[6]/ L17 VDD_IOA I2S0TX_CLK/ LCDVD[12] P0[7]/ L18 VDD_IOA I2S0TX_WS/ LCDVD[13] ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Power supply domain SPI2_DATIO/ A9 VDD_IOD MOSI1/ LCDVD[20] SPI2_DATIN/ A10 VDD_IOD MISO1/ LCDVD[21]/ GPI_27 SYSCLKEN/ G17 VDD_IOD LCDVD[15] SYSX_IN T17 VDD_OSC SYSX_OUT R15 VDD_OSC TS_XP R13 VDD_AD TS_YP U16 VDD_AD TST_CLK2 C6 VDD_IOB U1_RX/CAP1[0]/ K15 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Power supply domain U7_RX/ E17 VDD_IOD CAP0[0]/ LCDVD[10]/ GPI_23 U7_TX/ E18 VDD_IOD MAT1[1]/ LCDVD[11] USB_ATX_INT C4 VDD_IOC USB_DAT_VP/ D5 VDD_IOC U5_RX USB_I2C_SCL E5 VDD_IOC USB_I2C_SDA E6 VDD_IOC USB_OE_TP D6 VDD_IOC USB_SE0_VM/ C5 VDD_IOC U5_TX VDD_AD N12, VDD_AD N13 VDD_CORE ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Power supply domain VDD_PLL397 T16 VDD_PLL397 VDD_PLLHCLK R17 VDD_PLLHCLK VDD_PLLUSB P15 VDD_PLLUSB VDD_FUSE N14 VDD_FUSE VDD_RTC K14 VDD_RTC VDD_RTCCORE L13 VDD_RTCCORE VDD_RTCOSC N15 VDD_RTCOSC VSS_AD P13 - VSS_CORE G8, - G10, G12, H7, K12, L7, M9, M10, M12 ...
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... NXP Semiconductors Table 5. Digital I/O pad types Parameter I/O type Pin detail [1] See LPC32x0 User manual for details. Table 6. Supply domains Supply domain VDD_CORE VDD_COREFXD 1.2 V other core domains VDD_RTC VDD_AD VDD_EMC [1] VDD_IOA [1] VDD_IOB [1] VDD_IOC [1] VDD_IOD [1] The VDD_IOA, VDD_IOB, VDD_IOC, and VDD_IOD supply domains can be operated at a voltage independent of the other domains as long as all pins connected to the same peripheral are at the same voltage level ...
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... NXP Semiconductors 7. Functional description 7.1 CPU and subsystems 7.1.1 CPU NXP created the LPC3220/30/40/50 using an ARM926EJ-S CPU core that includes a Harvard architecture and a 5-stage pipeline. To this ARM core, NXP implemented instruction cache data cache and a Vector Floating Point coprocessor. The ARM926EJ-S core also has an integral Memory Management Unit (MMU) to provide the virtual memory capabilities required to support the multi-programming demands of modern operating systems ...
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... NXP Semiconductors 7.1.3.2 Embedded trace buffer The Embedded Trace Module (ETM) is connected directly to the ARM core. It compresses the trace information and exports it through a narrow trace port. An internal Embedded Trace Buffer (ETB) of 2048 × 24 bits captures the trace information under software debugger control. Data from the ETB is recovered by the debug software through the JTAG port ...
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... NXP Semiconductors 7.2.1 APB Many peripheral functions are accessed by on-chip APBs that are attached to the higher speed AHB. The APB performs reads and writes to peripheral registers in three peripheral clocks. 7.2.2 FAB Some peripherals are placed on a special bus called FAB that allows faster CPU access to those peripheral functions ...
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... NXP Semiconductors 4.0 GB off-chip memory 2.0 GB peripherals on AHB matrix slave port 7 1.0 GB peripherals on AHB matrix slave port 6 768 MB peripherals on AHB matrix slave port 5 on-chip memory 0.0 GB Fig 3. LPC3220/30/40/50 memory map LPC3220_30_40_50_1 Product data sheet RESERVED EMC_CS3 EMC_CS2 EMC_CS1 EMC_CS0 RESERVED EMC_DYSC1 ...
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... NXP Semiconductors 7.4 Internal memory 7.4.1 On-chip ROM The built- ROM contains a program which runs a boot procedure to load code from one of four external sources, UART5, SSP0 (SPI mode), EMC Static CS0 memory, or NAND FLASH. After reset, execution always begins from the internal ROM. The bootstrap software first reads the SERVICE input (GPI_1) ...
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... NXP Semiconductors 7.5.1.2 Single-Level Cell (SLC) NAND flash controller The SLC NAND flash controller interfaces to single-level NAND flash devices. DMA page transfers are supported, including a 20-byte DMA read and write FIFO. Hardware support for ECC (Error Checking and Correction) is included for the main data area. Software can correct a single bit error ...
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... NXP Semiconductors – extended wait • Power-saving modes dynamically control EMC_CKE[1:0] and EMC_CLK. • Dynamic memory self-refresh mode supported by software. • Controller supports and 8 k row address synchronous memory parts. That is, typical 512 MB, 256 MB, 128 MB, and 16 MB parts, with 8, 16 data bits per device. • ...
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... NXP Semiconductors packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU. The Ethernet DMA can access off-chip memory via the EMC, as well as the IRAM. The Ethernet block interfaces between an off-chip Ethernet PHY using the Media Independent Interface (MII) or Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial bus ...
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... NXP Semiconductors condition is indicated via status registers. An interrupt is also generated if enabled. The DMA controller when enabled transfers data between the endpoint buffer and the USB RAM. Features • Fully compliant with USB 2.0 full-speed specification. • Supports 32 physical (16 logical) endpoints. • ...
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... NXP Semiconductors • Supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) for dual-role devices under software control. HNP is partially implemented in hardware. • Provides programmable timers required for HNP and SRP. • Supports slave mode operation through AHB slave interface. ...
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... NXP Semiconductors 7.7 System functions To enhance the performance of the LPC3220/30/40/50 incorporates the following system functions, an Interrupt Controller (INTC), a watchdog timer, a millisecond timer, and several power control features. These functions are described in the following sections 7.7.1 Interrupt controller The interrupt controller is comprised of three basic interrupt controller blocks, supporting a total of 73 interrupt sources ...
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... NXP Semiconductors 7.7.4 Clocking and power control features 7.7.4.1 Clocking Clocking in the LPC3220/30/40/50 is designed to be versatile, so that system and peripheral requirements may be met, while allowing optimization of power consumption. Clocks to most functions may be turned off if not needed and some peripherals do this automatically. ...
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... NXP Semiconductors output to be used directly. The maximum PLL output frequency supported by the CPU is 266 MHz. The only output frequency supported by the USB PLL is 48 MHz, and the clock has strict requirements for nominal frequency (500 ppm) and jitter (500 ps). ...
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... NXP Semiconductors 7.8.1 UARTs The LPC3220/30/40/50 contains seven UARTs. Four are standard UARTs, and three are high-speed UARTs. 7.8.1.1 Standard UARTs The four standard UARTs are compatible with the INS16Cx50. These UARTs support rates up to 460800 bit/s from a 13 MHz peripheral clock. ...
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... NXP Semiconductors Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master. The SPI implementation on the LPC3220/30/40/50 does not support operation as a slave. ...
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... NXP Semiconductors There is a separate slave transmit FIFO. The slave transmit FIFO (TXS) and its level are only available when the controller is configured as a Master/Slave device and is operating in a multi-master environment. Separate TX FIFOs are needed in a multi-master because a controller might have a message queued for transmission when an external master addresses come a slave-transmitter, a second source of data is needed ...
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... NXP Semiconductors 7.9 Other peripherals In addition to the communication peripherals there are many general purpose peripherals available in the LPC3220/30/40/50. Here is a list of the general purpose peripherals. • GPI/O • Keyboard scanner • Touch screen controller and 10-bit Analog-to-Digital-Converter • Real-time clock • ...
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... NXP Semiconductors 7.9.2 Keyboard scanner The keyboard scanner function can automatically scan a keyboard keys × 8 matrix. In operation, the keyboard scanner’s internal state machine will normally idle state, with all KEY_ROWn pins set high, waiting for a change in the column inputs to indicate that one or more keys have been pressed. ...
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... NXP Semiconductors Two 32-bit match registers are readable and writable by the processor. A match will result in an interrupt provided that the interrupt is enabled. The ONSW output pin can also be triggered by a match event and cause an external power supply to turn on all of the operating voltages way to startup after power has been removed. ...
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... NXP Semiconductors – set LOW on match – set HIGH on match – toggle on match – do nothing on match 7.9.6 High-speed timer The high-speed timer block is clocked by the main peripheral clock. The clock is first divided down in a 16-bit programmable pre-scale counter which clocks a 32-bit timer/counter ...
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... NXP Semiconductors • 32-bit pulse-width (match) register • 10-bit dead-time register and an associated 10-bit dead-time counter • 32-bit capture register • Two PWM (match) outputs (pins MCOA0/1/2 and MCOB0/1/2) with opposite polarities • Period interrupt, pulse-width interrupt, and capture interrupt 8. Basic architecture The LPC3220/30/40/ general purpose ARM926EJ-S 32-bit microprocessor with instruction cache and data cache ...
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... NXP Semiconductors 9. Limiting values Table 7. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (1.2 V) DD(1V2) V external memory controller DD(EMC) supply voltage V analog supply voltage (3.3 V) DDA(3V3) V input/output supply voltage DD(IO) V analog input voltage IA V input voltage ...
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... NXP Semiconductors 10. Static characteristics Table 8. Static characteristics − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Conditions V supply voltage (1.2 V) core supply voltage for DD(1V2) full performance; 266 MHz (see VDD_CORE supply domain core supply voltage for normal performance; 208 MHz (see ...
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... NXP Semiconductors Table 8. Static characteristics …continued − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Conditions Power consumption in Run, direct Run, and Stop modes I Run mode supply T DD(run) current code executed from IRAM; all peripherals enabled I direct Run mode supply ...
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... NXP Semiconductors Table 8. Static characteristics …continued − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Conditions I RTC supply current VDD_RTC = DD(RTC) VDD_RTCCORE = VDD_RTCOSC = 1 Input pins and I/O pins configured as input V input voltage I V HIGH-level 1.8 V inputs IH input voltage 3.3 V inputs ...
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... NXP Semiconductors Table 8. Static characteristics …continued − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Conditions I HIGH-level short-circuit V OHS output current V I LOW-level short-circuit V OLS output current output impedance EMC pins V input voltage I V HIGH-level input voltage 1.8 V inputs IH 3.3 V inputs V LOW-level input voltage 1 ...
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... NXP Semiconductors Table 8. Static characteristics …continued − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Conditions I LOW-level V OL output current OFF-state V OZ output current no pull-up/down I HIGH-level short-circuit V OHS output current V I LOW-level short-circuit V OLS output current output impedance pins V input voltage ...
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... NXP Semiconductors Table 8. Static characteristics …continued − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Conditions V LOW-level 1.2 V outputs output voltage I HIGH-level V OH output current I LOW-level V OL output current I OFF-state V OZ output current no pull-up/down I HIGH-level short-circuit V OHS output current I LOW-level short-circuit ...
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... NXP Semiconductors 10.1 Minimum core voltage requirements Figure 4 shows the minimum core supply voltage that should be applied for a given core frequency on pin VDD_CORE to ensure stable operation of the LPC3220/30/40/50. 1.4 VDD_CORE (V) 1.2 1.0 0.8 160 Fig 4. Minimum required core supply voltage for different core frequencies 10 ...
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... NXP Semiconductors 10.4 Power consumption in Run mode Power consumption is shown in conditions from SDRAM. MMU and I-cache/D-cache are enabled. The VFP is turned on but not used. I touchscreen ADC, and UART3 are turned on. All other peripherals are turned off. The AHB clock HCLK is identical to the core clock for frequencies up to 133 MHz, which is the maximum allowed HCLK frequency ...
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... NXP Semiconductors 10.5 ADC static characteristics Table 10. ADC static characteristics ° 3 unless otherwise specified; ADC clock frequency 4.5 MHz. DDA(3V3) amb Symbol Parameter V analog input voltage IA C analog input capacitance ia E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error ( (4) Integral non-linearity (E ). L(adj) (5) Center of a step of the actual transfer curve. Fig 6. ADC characteristics LPC3220_30_40_50_1 Product data sheet ...
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... NXP Semiconductors 11. Dynamic characteristics 11.1 Clocking and I/O port pins Table 11. Dynamic characteristics − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Reset t external RESET pulse width w(RESET)ext External clock f external clock frequency ext Port pins t rise time r t fall time ...
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... NXP Semiconductors Table 12. Dynamic characteristics: static external memory interface ° pF 1 amb DD(EMC) Symbol Parameter t WE LOW to WE HIGH time WELWEH t BLS LOW to BLS HIGH time BLSLBLSH t WE HIGH to address invalid time WEHANV t WE HIGH to data invalid time WEHDNV t BLS HIGH to address invalid time ...
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... NXP Semiconductors EMC_A[23:0] EMC_CS[3:0] EMC_D[31:0] EMC_WR EMC_BLS[3:0] Fig 8. External memory write access LPC3220_30_40_50_1 Product data sheet t CSLAV t CSLDV t WELDV t WEHDNV t CSLWEL t WELWEH t BLSHDNV t CSLBLSL t BLSLBLSH All information provided in this document is subject to legal disclaimers. Rev. 01.03 — 16 March 2010 LPC3220/30/40/50 16/32-bit ARM microcontrollers ...
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... NXP Semiconductors 11.3 SDR SDRAM Controller Table 13. EMC SDR SDRAM memory interface dynamic characteristics − ° ° pF +85 C, unless otherwise specified. L amb Symbol Parameter f operating frequency oper t clock cycle time LOW-level width HIGH-level width CH t control valid delay time d(V)ctrl t control hold time ...
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... NXP Semiconductors 11.4 DDR SDRAM controller Table 14. EMC DDR SDRAM memory interface dynamic characteristics ° pF unless otherwise specified. L amb Symbol Parameter f operating frequency oper t clock cycle time LOW-level width HIGH-level width CH t control valid delay time d(V)ctrl t control hold time h(ctrl) ...
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... NXP Semiconductors EMC_CLK EMC control and address signals Fig 10. DDR control timing parameters EMC_CLK command WRITE EMC_DQS[1:0] EMC_D[15:0], EMC_DQM[1:0] Fig 11. DDR write timing parameters EMC_CLK command READ EMC_DQSm (1) delayed EMC_DQSm EMC_D[31:0] (1) The delay of the EMC_DQSm signal is determined by the DQS_DELAY settings. See LPC32x0 user manual, External Memory Controller Chapter, section DDR DQS delay calibration for details on configuring this value ...
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... NXP Semiconductors 11.5 USB controller Table 15. Dynamic characteristics USB digital I/O pins − ° ° 3 +85 C, unless otherwise specified. DD(IO) amb Symbol Parameter t bus turnaround time (I/O) TIO t bus turnaround time (O/I) TOI [1] Parameters are valid over operating temperature range unless otherwise specified. ...
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... NXP Semiconductors Fig 14. SD card pin interface timing 11.7 MLC NAND flash memory controller Table 17. Dynamic characteristics of the MLC NAND flash memory controller − ° ° +85 C. amb Symbol Parameter t CE LOW to RE LOW time CELREL t RE cycle time HIGH hold time ...
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... NXP Semiconductors FLASH_RDY (R/B) Fig 15. MLC NAND flash controller write timing (writing to NAND flash) Fig 16. MLC NAND flash controller read timing (reading from NAND flash) 11.8 SLC NAND flash memory controller Table 18. Dynamic characteristics of SLC NAND flash memory controller − ° ...
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... NXP Semiconductors Table 18. Dynamic characteristics of SLC NAND flash memory controller − ° ° +85 C. amb Symbol Parameter t CE access time CEA t CE set-up time hold time CH t CLE set-up time CLS t CLE hold time CLH t CLE to RE delay time CLR t data hold time ...
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... NXP Semiconductors Table 18. Dynamic characteristics of SLC NAND flash memory controller − ° ° +85 C. amb Symbol Parameter t WE HIGH hold time HIGH to RE LOW time WHR t WE pulse width HIGH to R/B LOW time REHRBL [ 1/HCLK HCLK [2] Rsu = bitfield R_SETUP[3:0] in register SLC_TAC[3:0] for reads ...
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... NXP Semiconductors t t ALS ALH FLASH_ALE t t CLS CLH FLASH_CLE FLASH_RDY FLASH_WR FLASH_RD command FLASH_IO[7: FLASH_CE command Fig 18. MLC NAND Flash memory read timing (reading from NAND flash) LPC3220_30_40_50_1 Product data sheet t t ALS ALH t CLS CLR address CEA address All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors FLASH_CE t t CLS CLH FLASH_CLE t WP FLASH_WR FLASH_RD FLASH_IO[7:0] Fig 19. MLC NAND flash memory status timing 11.9 SPI and SSP Controller 11.9.1 SPI Table 19. Dynamic characteristics of SPI pins on SPI master controller − ° ° +85 C. amb Symbol Parameter Common to SPI1 and SPI2 ...
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... NXP Semiconductors 11.9.2 Timing diagrams for SPI and SSP (in SPI mode) Fig 20. SPI master timing (CPHA = 0) SCK0/1 (CPOL = 0) SCK0/1 (CPOL = 1) SPI1/2_DATAIO or SPI1/2_DATAIN or Fig 21. SPI master timing (CPHA = 1) LPC3220_30_40_50_1 Product data sheet T SPICYC SPI1/2_CLK or SCK0/1 (CPOL = 0) SPI1/2_CLK or SCK0/1 (CPOL = 1) t SPIQV SPI1/2_DATAIO or ...
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... NXP Semiconductors Fig 22. SPI slave timing (CPHA = 0) SCK0/1 (CPOL = 0) SCK0/1 (CPOL = 1) SPI1/2_DATAIO or SPI1/2_DATAIN or Fig 23. SPI slave timing (CPHA = 1) LPC3220_30_40_50_1 Product data sheet T SPICYC SPI1/2_CLK or SCK0/1 (CPOL = 0) SPI1/2_CLK or SCK0/1 (CPOL = 1) SPI1/2_DATAIO or DATA VALID MOSI0/1 t SPIQV SPI1/2_DATAIN or DATA VALID MISO0/1 T SPICYC SPI1/2_CLK or SPI1/2_CLK or ...
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... NXP Semiconductors 12. Package outline TFBGA296: plastic thin fine-pitch ball grid array package; 296 balls ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.4 0.80 0.5 15.1 mm 1.2 0.3 0.65 0.4 14.9 OUTLINE VERSION IEC SOT1048-1 Fig 24. Package outline SOT1048-1 (TFBGA296) ...
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... NXP Semiconductors 13. Abbreviations Table 20. Abbreviations Acronym ADC AHB AMBA APB BSDL CISC DDR SDRAM DMA DSP ETM FAB FIFO FIQ GPIO I/O IRQ HS IrDA JTAG LCD MAC MIIM OHCI OTG PHY PLL PWM RAM RMII SE0 SDR SDRAM SPI SSI SSP ...
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... NXP Semiconductors Table 20. Abbreviations Acronym UART USB VFP LPC3220_30_40_50_1 Product data sheet …continued Description Universal Asynchronous Receiver/Transmitter Universal Serial Bus Vector Floating Point processor All information provided in this document is subject to legal disclaimers. Rev. 01.03 — 16 March 2010 LPC3220/30/40/50 16/32-bit ARM microcontrollers © ...
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... NXP Semiconductors 14. Revision history Table 21. Revision history Document ID Release date LPC3220_30_40_50_1.03 <tbd> • Modifications: Power supply domain for pins SYSX_IN and SYSX_OUT pins corrected in • Power supply domain for pin VDD_OSC corrected in • Description of DEBUG pin updated in • Document template updated. ...
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... NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 7 Functional description . . . . . . . . . . . . . . . . . . 23 7.1 CPU and subsystems . . . . . . . . . . . . . . . . . . . 23 7.1.1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1.2 Vector Floating Point (VFP) coprocessor . . . . 23 7 ...
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... NXP Semiconductors 15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 15.4 Trademarks Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 LPC3220/30/40/50 16/32-bit ARM microcontrollers Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp ...