LPC3230FET296,551 NXP Semiconductors, LPC3230FET296,551 Datasheet - Page 52

• Manufacturer Part Number: LPC3230FET296,551
• Description: IC ARM9 MCU 256K 296-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC32x0r

Specifications of LPC3230FET296,551

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 266MHz
• Connectivity: EBI/EMI, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, Motor Control PWM, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: ROMless
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 296-TFBGA
• Processor Series: LPC32
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 256 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 6
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4531; 935287119551

NXP Semiconductors
LPC3220_30_40_50_1
Product data sheet
10.4 Power consumption in Run mode
Power consumption is shown in
conditions from SDRAM. MMU and I-cache/D-cache are enabled. The VFP is turned on
but not used. I
touchscreen ADC, and UART3 are turned on. All other peripherals are turned off.
The AHB clock HCLK is identical to the core clock for frequencies up to 133 MHz, which is
the maximum allowed HCLK frequency. For higher core frequencies, the HCLK PLL
output must be divided by 2 to obtain an HCLK frequency lower than or equal to 133 MHz
resulting in correspondingly lower power consumption by the AHB peripherals.
Fig 5.
(1) WinCE running from SDRAM; playing wmv file at 20 frames/s, 32 kHz mono.
(2) WinCE running from SDRAM; playing mp3 file at 128 kbit/s, stereo.
(3) WinCE running from SDRAM; no application running.
I
DD(run)
(mA)
160
120
80
40
Conditions: T
VDD_CORE = 1.35 V for core frequencies > 208 MHz; V
Core current versus core frequency for WinCE applications
0
40
2
S-interface (channel 1), LCD, SLC NAND controller, I
All information provided in this document is subject to legal disclaimers.
amb
Rev. 01.03 — 16 March 2010
= 25 °C; VDD_CORE = 1.2 V for core frequencies ≤ 208 MHz;
Figure 5
120
HCLK = 133 MHz
HCLK = 72 MHz
for WinCE applications running under typical
VDD_CORE =
1.2 V
LPC3220/30/40/50
200
DD(IO)
16/32-bit ARM microcontrollers
core frequency (MHz)
= 1.8 V.
VDD_CORE =
1.35 V
2
C1-bus, SD card,
002aae762
© NXP B.V. 2010. All rights reserved.
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(2)
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