LPC3230FET296,551 NXP Semiconductors, LPC3230FET296,551 Datasheet - Page 55

• Manufacturer Part Number: LPC3230FET296,551
• Description: IC ARM9 MCU 256K 296-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC32x0r

Specifications of LPC3230FET296,551

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 266MHz
• Connectivity: EBI/EMI, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, Motor Control PWM, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: ROMless
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 296-TFBGA
• Processor Series: LPC32
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 256 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 6
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4531; 935287119551

NXP Semiconductors
11. Dynamic characteristics
Table 11.
T
[1]
[2]
[3]
Table 12.
C
LPC3220_30_40_50_1
Product data sheet
Symbol
Reset
t
External clock
f
Port pins
t
t
Symbol
Common to read and write cycles
T
t
Read cycle parameters
t
t
t
t
t
t
t
t
t
t
t
t
Write cycle parameters
t
t
t
t
w(RESET)ext
ext
r
f
CSLAV
OELAV
BLSLAV
CSLOEL
CSLBLSL
OELOEH
BLSLBLSH
su(DQ)
h(DQ)
CSHOEH
CSHBLSH
OEHANV
BLSHANV
CSLDV
CSLWEL
CSLBLSL
WELDV
amb
L
CLCL
= 25 pF, T
Parameters are valid over operating temperature range unless otherwise specified.
After supply voltages are stable
Supplied by an external crystal.
=
−
40
°
Dynamic characteristics
Dynamic characteristics: static external memory interface
Parameter
clock cycle time
CS LOW to address valid time
OE LOW to address valid time
BLS LOW to address valid time
CS LOW to OE LOW time
CS LOW to BLS LOW time
OE LOW to OE HIGH time
BLS LOW to BLS HIGH time
data input/output set-up time
data input/output hold time
CS HIGH to OE HIGH time
CS HIGH to BLS HIGH time
OE HIGH to address invalid time
BLS HIGH to address invalid time
CS LOW to data valid time
CS LOW to WE LOW time
CS LOW to BLS LOW time
WE LOW to data valid time
C to +85
amb
11.1 Clocking and I/O port pins
11.2 Static memory controller
= 20
Parameter
external RESET pulse width
external clock frequency
rise time
fall time
°
°
C, unless otherwise specified.
C, V
DD(EMC)
= 1.8 V, 2.5 V, or 3.3 V.
All information provided in this document is subject to legal disclaimers.
Rev. 01.03 — 16 March 2010
[1]
Notes Min
Conditions
[2][3]
[2][3]
[1]
[2]
[2]
[2]
[6]
[6]
[4]
[4]
[4]
7.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Typ
9.6
0
0 − WAITOEN × T
0 − WAITOEN × T
0 + WAITOEN × T
0 + WAITOEN × T
(WAITRD − WAITOEN + 1) × T
(WAITRD − WAITOEN + 1) × T
8.4
0
0
0
1 × T
1 × T
0
(WAITWEN + 1) × T
(WAITWEN + 1) × T
0 − (WAITWEN + 1) × T
[2]
[3]
CLCL
CLCL
Min
10
1
-
-
LPC3220/30/40/50
16/32-bit ARM microcontrollers
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
Typ
-
13
5
5
CLCL
CLCL
CLCL
© NXP B.V. 2010. All rights reserved.
Max
-
20
-
-
Max
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
55 of 77
Unit
ms
MHz
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns