LPC3230FET296,551 NXP Semiconductors, LPC3230FET296,551 Datasheet - Page 58

• Manufacturer Part Number: LPC3230FET296,551
• Description: IC ARM9 MCU 256K 296-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC32x0r

Specifications of LPC3230FET296,551

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 266MHz
• Connectivity: EBI/EMI, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, Motor Control PWM, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: ROMless
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 296-TFBGA
• Processor Series: LPC32
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 256 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 6
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4531; 935287119551

NXP Semiconductors
Table 13.
C
[1]
[2]
[3]
[4]
[5]
[6]
LPC3220_30_40_50_1
Product data sheet
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
oper
CK
CL
CH
d(V)ctrl
h(ctrl)
d(AV)
h(A)
d(QV)
h(Q)
su(D)
h(D)
QZ
L
= 25 pF, T
Parameters are valid over operating temperature range unless otherwise specified.
Typical values valid for EMC pads set to fast slew rate: VDD_EMC = 1.8 V, VDD_CORE = 1.2 V or slower slew rate: VDD_EMC = 3.3 V,
VDD_CORE = 1.2 V (see SDRAMCLK_CTRL register in the LPC32x0 User manual).
All min or max values valid for EMC pads set to fast slew rate: VDD_EMC = 1.8 V, VDD_CORE = 1.2 V or slower slew rate: VDD_EMC
= 3.3 V, VDD_CORE = 1.2 V.
f
Applies to signals: EMC_DQM[3:0], EMC_DYCSm, EMC_RAS, EMC_CAS, EMC_WR, EMC_CKEm.
CMD_DLY = COMMAND_DELAY bitfield in SDRAMCLK_CTRL[18:14] register, see External memory controller (EMC) chapter in
LPC32x0 User manual.
oper
= 1/t
EMC SDR SDRAM memory interface dynamic characteristics
CK.
amb
Parameter
operating frequency
clock cycle time
CK LOW-level width
CK HIGH-level width
control valid delay time
control hold time
address valid delay time
address hold time
data output valid delay time
data output hold time
data input set-up time
data input hold time
data output high-impedance time
11.3 SDR SDRAM Controller
=
−
40
°
C to +85
Fig 9.
°
C, unless otherwise specified.
SDR SDRAM signal timing
All information provided in this document is subject to legal disclaimers.
output signal (O)
input signal (I)
EMC_CLK
Rev. 01.03 — 16 March 2010
[5][6]
[5][6]
[4]
[6]
[6]
[6]
[6]
-
Min
7.5
-
-
-
-
-
-
-
t
d(V)ctrl
[1][3]
, t
Typical
104
9.6
4.8
4.8
(CMD_DLY × 0.25) + 2.7
(CMD_DLY × 0.25) + 1.2
(CMD_DLY × 0.25) + 3.2
(CMD_DLY × 0.25) + 1.2
(CMD_DLY × 0.25) + 3.5
(CMD_DLY × 0.25) + 1.2
0.6
0.9
-
t
d(AV)
CH
, t
d(QV)
[2]
t
CK
LPC3220/30/40/50
t
CL
t
su(D)
16/32-bit ARM microcontrollers
t
t
h(ctrl)
h(D)
, t
t
002aae420
QZ
h(Q)
, t
h(A)
Max
133
-
-
-
-
-
-
-
-
< t
© NXP B.V. 2010. All rights reserved.
CK
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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