EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 254

IC ARM9 SOC ENH UNIV 352PBGA

EP9315-CBZ

Manufacturer Part Number
EP9315-CBZ
Description
IC ARM9 SOC ENH UNIV 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9315-CBZ

Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Cpu Speed
200MHz
No. Of Timers
5
Digital Ic Case Style
BGA
Supply Voltage Range
1.65V To 1.94V, 3V To 3.6V
Embedded Interface Type
SPI
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
Case
BGA
Dc
06+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
Other names
598-1139

Available stocks

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Part Number
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Quantity
Price
Part Number:
EP9315-CBZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
EP9315-CBZ
Manufacturer:
ALTERA
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Part Number:
EP9315-CBZ
Manufacturer:
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Quantity:
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Quantity:
48
7
CursorBlinkRateCtrl
7-72
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
31
15
Address: 0x8003_0224
Default: 0x0000_0000
Definition: Blink Rate Control register
Bit Descriptions:
30
14
29
13
RSVD
28
12
RSVD:
EN:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
When Dual Scan mode is enabled by writing DSCAN = ‘1’
in the
this field specifies the starting vertical Y location (in the
lower half of the display) of the cursor image. The value is
compared to the vertical line counter and it should be
specified to be between the active start and active stop
vertical line values.
The cursor hardware will clip the cursor at the bottom of
the display. To prevent cursor distortion, a new Y Location
value will not be used until the next frame.
Reserved - Unknown during read
Enable - Read/Write
Writing a ‘1’ to this bit enables hardware cursor blinking
and enables the blink rate counter. Writing a ‘0’ to this bit
disables hardware cursor blinking and disables the blink
rate counter:
0 - Hardware cursor blinking not enabled
1 - Hardware cursor blinking enabled
When EN = ‘1’ and the 2-bit cursor pixel fetched from
SDRAM is ‘10’,
the blink toggle and
of the blink toggle.
When EN = ‘1’ and the 2-bit cursor pixel fetched from
SDRAM is ‘11’,
of the blink toggle and
part of the blink toggle.
EN
24
8
PixelMode
RSVD
23
7
CursorBlinkColor1,
CursorColor2,
register, the Y Location value written to
22
6
CursorColor1,
CursorColor1,
21
5
20
4
is used for the ‘on’ part of
RATE
is used for the ‘off’ part
is used for the ‘on’ part
19
3
is used for the ‘off’
18
2
17
1
DS785UM1
16
0

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