EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 288
EP9315-CBZ
Manufacturer Part Number
EP9315-CBZ
Description
IC ARM9 SOC ENH UNIV 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9315-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Cpu Speed
200MHz
No. Of Timers
5
Digital Ic Case Style
BGA
Supply Voltage Range
1.65V To 1.94V, 3V To 3.6V
Embedded Interface Type
SPI
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
Case
BGA
Dc
06+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1139
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9315-CBZ
Manufacturer:
CIRRUS
Quantity:
20 000
- Current page: 288 of 824
- Download datasheet (13Mb)
8
8-24
Graphics Accelerator
EP93xx User’s Guide
31
15
Default:
Mask:
Definition:
Bit Descriptions:
Address:
30
14
29
13
28
12
0x0000_0000
0x001F_001F
Destination Pixel Start/End register
RSVD:
EPEL:
SPEL:
BLKSRCSTRT
0x8004_0008 - Read/Write
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved - Unknown during read
Destination Pixel Location - Read/Write
For the ending pixel (at the ending X-Y coordinate of the
1st scan line) of the destination image for a block copy, the
value in this field specifies where the beginning bit of the
ending pixel is located in a 32-bit word. For example, if the
beginning bit of an 8-bit pixel is located at bit 24 of a 32-bit
word, EPEL = 0x18.
The EPEL field and the ADR field in the
register together define the destination ending pixel’s
address in the SDRAM frame buffer. Granularity must be a
multiple of the pixel size in all video display modes. For
example,.acceptable values in 8 bpp mode are 0x00,
0x08, 0x10, and 0x18.
Source Pixel Location - Read/Write
For the starting pixel (at the starting X-Y coordinate of the
1st scan line) of the destination image for a block copy, the
value in this field specifies where the beginning bit of the
pixel is located in a 32-bit word. For example, if the
beginning bit of a 16-bit pixel is located at bit 16 of a 32-bit
word, PEL = 0x10.
The SPEL field and the ADR field in the
register together define the destination starting pixel’s
address in the SDRAM frame buffer. Granularity must be a
multiple of the pixel size in all video display modes. For
example,.acceptable values in 8 bpp mode are 0x00,
0x08, 0x10, and 0x18.
ADR
24
8
ADR
23
7
22
6
21
5
20
4
19
3
“BLKDESTSTRT”
“BLKDESTSTRT”
18
2
17
1
DS785UM1
NA
16
0
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