EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 782

IC ARM9 SOC ENH UNIV 352PBGA

EP9315-CBZ

Manufacturer Part Number
EP9315-CBZ
Description
IC ARM9 SOC ENH UNIV 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9315-CBZ

Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Cpu Speed
200MHz
No. Of Timers
5
Digital Ic Case Style
BGA
Supply Voltage Range
1.65V To 1.94V, 3V To 3.6V
Embedded Interface Type
SPI
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
Case
BGA
Dc
06+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
Other names
598-1139

Available stocks

Company
Part Number
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Quantity
Price
Part Number:
EP9315-CBZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
EP9315-CBZ
Manufacturer:
ALTERA
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Part Number:
EP9315-CBZ
Manufacturer:
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Quantity:
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Quantity:
48
27
IDEMDMAOp
IDEUDMAOp
27-12
IDE Interface
EP93xx User’s Guide
31
15
31
15
Address:
Default:
Definition:
Bit Descriptions:
Address:
Note: At most, one of the above 3 bits should be set to 1 at any time. If more than one is set, the
30
14
30
14
results will be unpredictable, and the data invalid.
29
13
29
13
28
12
28
12
MODE:
WST:
0x800A_0008 Read/Write
0x0000_0000
IDE MDMA Configuration Register.
RSVD:
MEN:
RWOP:
0x800A_000C - Read/Write
27
27
11
11
26
10
26
10
Copyright 2007 Cirrus Logic
25
25
9
9
Speed mode number. (0 to 4 defined for PIO, 0 to 2
defined for MDMA, 0 to 4 defined for UDMA).
Wait State for Turn. Number of HCLK cycles to hold the
data bus after a PIO write operation.
Reserved. Unknown during read, ignored during write.
Enable Multiword DMA operation.
1 - to start MDMA
0 - to terminate MDMA by the host.
Read or write operation selection:
0 - Read
1 - Write.
RSVD
RSVD
24
24
8
8
RSVD
RSVD
23
23
7
7
22
22
6
6
21
21
5
5
20
20
4
4
19
19
3
3
18
18
2
2
RWOP
RWOP
17
17
1
1
DS785UM1
MEN
UEN
16
16
0
0

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