EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 488

• Manufacturer Part Number: EP9315-CBZ
• Description: IC ARM9 SOC ENH UNIV 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Cpu Speed: 200MHz
• No. Of Timers: 5
• Digital Ic Case Style: BGA
• Supply Voltage Range: 1.65V To 1.94V, 3V To 3.6V
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Case: BGA
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1139

12
SMCBCR[7:0]
12-10
Static Memory Controller
EP93xx User’s Guide
12.6.1 Bank Configuration Registers
12.6 Registers
RSVD
31
15
Address:
Default:
Definition:
EBIBRK
DIS
30
14
WST2
29
13
MW
0x8008_000C
0x8008_001C
0x8008_002C
0x8008_003C
0x8008_0000
0x8008_0004
0x8008_0008
0x8008_0010
0x8008_0014
0x8008_0018
0x8008_0020
0x8008_0024
0x8008_0028
0x8008_0030
0x8008_0034
0x8008_0038
0x8008_0040
Address
28
12
SMCBCR0: 0x8008_0000 - Read/Write
SMCBCR1: 0x8008_0004 - Read/Write
SMCBCR2: 0x8008_0008 - Read/Write
SMCBCR3: 0x8008_000C - Read/Write
SMCBCR6: 0x8008_0018 - Read/Write
SMCBCR7: 0x8008_001C - Read/Write
0x2000_FBE0
SMC Bank Configuration registers
These registers are used to specify the characteristics and timing for each of
the memory banks, respectively.
Table 12-8. Static Memory Controller (SMC) Register Map
PME
27
11
BLE
WP
26
10
"SMCBCR[7:0]"
"SMCBCR[7:0]"
"SMCBCR[7:0]"
"SMCBCR[7:0]"
"SMCBCR[7:0]"
"SMCBCR[7:0]"
"SMCBCR[7:0]"
"PCCommon"
"PCMCIACtrl"
"PCAttribute"
Copyright 2007 Cirrus Logic
WPERR
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
"PCIO"
Name
25
9
24
8
WST1
23
7
(See individual bank configuration
Bank Configuration Register 0
Bank Configuration Register 1
Bank Configuration Register 2
Bank Configuration Register 3
Bank Configuration Register 6
Bank Configuration Register 7
22
Common Space Register
6
Attribute Space Register
I/O Space Register
registers below)
Control Register
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
21
5
RSVD
RSVD
20
4
19
3
18
2
IDCY
17
1
DS785UM1
16
0