EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 628

• Manufacturer Part Number: EP9315-CBZ
• Description: IC ARM9 SOC ENH UNIV 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Cpu Speed: 200MHz
• No. Of Timers: 5
• Digital Ic Case Style: BGA
• Supply Voltage Range: 1.65V To 1.94V, 3V To 3.6V
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Case: BGA
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1139

17
MISR
17-32
IrDA
EP93xx User’s Guide
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
0x808B_0080 - Read/Write
0x0000_0000
MIR Status Register.
RSVD:
RFL:
RIL:
RFC:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
Receive Frame Lost. Set to a “1” when a ROR occurred at
the start of a new frame, before any data for the frame
could be put into the receive FIFO. This bit is cleared by
writing a “1” to this bit. This occurs if the last entry in the
FIFO already contains a valid EOF bit from a previous
frame when a FIFO overrun occurs. The ROR bit cannot
be placed into the FIFO and all data associated with the
frame is lost.
Receive Information Buffer Lost. Set to a “1” when the last
data for a frame is read from the receive FIFO and the
RFC bit is still set from a previous end of frame. This bit is
cleared by writing a “1” to this bit. This is triggered if the
RFC bit is already set before the last data from a frame is
read from the IrData register. It indicates that the data from
the IrRIB register was lost. This can occur if the CPU does
not respond to the RFC interrupt before another (short)
frame completes and is read from the IrData register by
the DMA controller.
Received Frame Complete. Set to “1” when the last data
for a frame is read from the receive FIFO (via the IrData
register). This event also triggers the IrRIB to load the
IrFlag and byte count. This bit is cleared when the IrRIB
register is read.
24
8
RSVD
23
7
RFL
22
6
RIL
21
5
RFC
20
4
RFS
19
3
TAB
18
2
TFC
17
1
DS785UM1
TFS
16
0