EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 706

• Manufacturer Part Number: EP9315-CBZ
• Description: IC ARM9 SOC ENH UNIV 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Cpu Speed: 200MHz
• No. Of Timers: 5
• Digital Ic Case Style: BGA
• Supply Voltage Range: 1.65V To 1.94V, 3V To 3.6V
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Case: BGA
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1139

22
AC97RGIS
22-18
AC’97 Controller
EP93xx User’s Guide
31
15
Address:
Definition:
Bit Descriptions:
30
14
29
13
28
12
0x8088_008C - Read Only
Raw Global Interrupt Status Register. The AC’97 raw global interrupt status
register is a read/write register that gives the status of various functions
outside of the FIFO functionality within the controller.
RSVD:
SLOT2TXCOMPLETE:Set when the AC97S2Data register has completed
CODECREADY:
WINT:
GPIOINT:
GPIOTXCOMPLETE:GPIO Transmission Complete. Set when a new value to
SLOT2RXVALID: The AC97S2Data register has new data that has not been
SLOT1TXCOMPLETE:Set when the AC97S1Data register has completed
RSVD
27
11
26
10
25
9
Copyright 2007 Cirrus Logic
24
Reserved. Unknown During Read.
This bit is set to “1” during a wakeup when the codec
RAW Wake-up Interrupt Status. If this bit is set to “1”. The
The GPIOINT shows the raw status of the GPIOINT bit
8
transmission. This bit is cleared when data is in the
register to be transmitted.
indicates that it is ready by setting bit 15 of Slot0. It is
cleared by writing to Bit1 of the AC97EOI Register.
RAW Wake-up interrupt is asserted. This bit is cleared
with a write to the AC97EOI register.
(slot 12 bit 0) in the receive frame, which is stored in
the AC97S12Data register. This bit is cleared when
the AC97S12Data register is read.
the AC97S12Data register has completed
transmission. Cleared when data is placed in the
register to be transmitted.
read. Reading the data in the AC97S2Data register
clears this bit.
transmission. This bit is cleared when data is written
to the AC97S1Data register to be transmitted.
23
7
RSVD
COMPLETE
SLOT2TX
22
6
CODEC
READY
21
5
WINT
20
4
GPIO
INT
19
3
COMPLETE
GPIOTX
18
2
SLOT2RX
VALID
17
1
DS785UM1
COMPLETE
SLOT1TX
16
0