EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 778
![IC ARM9 SOC ENH UNIV 352PBGA](/photos/12/23/122387/ep9315-cbz_sml.jpg)
EP9315-CBZ
Manufacturer Part Number
EP9315-CBZ
Description
IC ARM9 SOC ENH UNIV 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9315-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Cpu Speed
200MHz
No. Of Timers
5
Digital Ic Case Style
BGA
Supply Voltage Range
1.65V To 1.94V, 3V To 3.6V
Embedded Interface Type
SPI
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
Case
BGA
Dc
06+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1139
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9315-CBZ
Manufacturer:
CIRRUS
Quantity:
20 000
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27
27-8
27.2.7.3.1 General Note
27.2.7.3.2 Multi-word DMA
IDE Interface
EP93xx User’s Guide
27.2.7.3 IDE DMA Programming Considerations
This is a general guideline for programming the DMA controller to properly interact with the
IDE controller without receiving malformed data. All cases assume the DMA controller is
capable of burst read or burst write operations. Non-ideal DMA controllers may be able to
avoid wait-states due to less than optimal bus utilization.
Please verify that the DMA controller will ignore DMA requests if it's transfer counter register
has gone to zero. If this is not the case, the DMA controller must be configured to time out
based on the wait-state table in
allowed.
Follow the wait-state number listed in the wait-state table in
word bursts are not allowed.
Note: This is the number of wait states required by the IDE Controller to deassert the DMA
Multi-word DMA Read from IDE Controller:
Controller request line after each word transfer is complete.
Wait States:
Multi-word DMA Write to IDE Controller:
Ultra DMA Read from IDE Controller:
Read
Write
Ultra DMA Write to IDE Controller:
Table 27-3. Wait State Value for the DMA M2M Register Control.PWSC
Operation
Table 27-4. HCLK Cycles to De-assert DMA Request
Multi-Word DMA Request
Copyright 2007 Cirrus Logic
Table 27-3
0
3
HCLK Cycle
0
1
0
1
0
1
2
3
0
1
2
and
Table
AHB write command
DMAide deasserts
AHB read command
AHB read data, DMAide deasserts
AHB write command
Data stored in IDE register
Data stored in FIFO, FIFO status updates
DMAide deasserts
AHB read command
AHB read data, word counter updates
DMAide deasserts
27-4. Quad-word bursts are not
Table 27-3
Ultra DMA Request
Event
1
2
and
Table
27-4. Quad-
DS785UM1
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