EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 8

• Manufacturer Part Number: EP9315-CBZ
• Description: IC ARM9 SOC ENH UNIV 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Cpu Speed: 200MHz
• No. Of Timers: 5
• Digital Ic Case Style: BGA
• Supply Voltage Range: 1.65V To 1.94V, 3V To 3.6V
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Case: BGA
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1139

EP93xx User’s Guide
Chapter 10. DMA Controller................................................................................ 10-1
Chapter 11. Universal Serial Bus Host Controller ............................................ 11-1
viii
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1
10.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-20
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1
11.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1
10.1.1 DMA Features List.......................................................................................................10-1
10.1.2 Managing Data Transfers Using a DMA Channel .......................................................10-2
10.1.3 DMA Operations ..........................................................................................................10-3
10.1.4 Internal M2P or P2M AHB Master Interface Functional Description............................10-4
10.1.5 M2M AHB Master Interface Functional Description.....................................................10-5
10.1.6 AHB Slave Interface Limitations ..................................................................................10-6
10.1.7 Interrupt Interface ........................................................................................................10-6
10.1.8 Internal M2P/P2M Data Unpacker/Packer Functional Description ..............................10-6
10.1.9 Internal M2P/P2M DMA Functional Description ..........................................................10-7
10.1.10 M2M DMA Functional Description ...........................................................................10-10
10.1.11 DMA Data Transfer Size Determination ..................................................................10-17
10.1.12 Buffer Descriptors....................................................................................................10-18
10.1.13 Bus Arbitration .........................................................................................................10-19
10.2.1 DMA Controller Memory Map ....................................................................................10-20
10.2.2 Internal M2P/P2M Channel Register Map .................................................................10-21
11.1.1 Features ......................................................................................................................11-1
11.2.1 Data Transfer Types....................................................................................................11-2
11.2.2 Host Controller Interface..............................................................................................11-3
11.2.3 Host Controller Driver Responsibilities ........................................................................11-6
Handshaking Signals ................................................................................................10-6
10.1.3.1 Memory-to-Memory Channels ...................................................................10-3
10.1.3.2 Memory-to-Peripheral Channels ................................................................10-4
10.1.5.1 Software Trigger Mode ..............................................................................10-5
10.1.5.2 Hardware Trigger Mode for Internal Peripherals (SSP and IDE) and
10.1.5.3 Hardware Trigger Mode for External Peripherals with
10.1.9.1 Internal M2P/P2M DMA Buffer Control Finite State Machine ....................10-7
10.1.9.2 Data Transfer Initiation and Termination ...................................................10-9
10.1.10.1 M2M DMA Control Finite State Machine ...............................................10-10
10.1.10.2 M2M Buffer Control Finite State Machine..............................................10-12
10.1.10.3 Data Transfer Initiation ..........................................................................10-13
10.1.10.4 Data Transfer Termination.....................................................................10-15
10.1.10.5 Memory Block Transfer..........................................................................10-16
10.1.10.6 Bandwidth Control .................................................................................10-16
10.1.10.7 External DMA Request (DREQ) Mode ..................................................10-16
10.1.11.1 Software Initiated M2M and M2P/P2M Transfers ..................................10-17
10.1.11.2 Hardware-Initiated M2M Transfers ........................................................10-18
10.1.12.1 Internal M2P/P2M Channel Rx Buffer Descriptors ................................10-19
10.1.12.2 Internal M2P/P2M Channel Tx Buffer Descriptors.................................10-19
10.1.12.3 M2M Channel Buffer Descriptors...........................................................10-19
11.2.2.1 Communication Channels..........................................................................11-3
11.2.2.2 Data Structures..........................................................................................11-4
11.2.3.1 Host Controller Management.....................................................................11-6
11.2.3.2 Bandwidth Allocation .................................................................................11-6
11.2.3.3 List Management .......................................................................................11-7
11.2.3.4 Root Hub....................................................................................................11-7
for External Peripherals without Handshaking Signals ...........................................10-6
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Copyright 2007 Cirrus Logic, Inc.
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