EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 686

• Manufacturer Part Number: EP9315-CBZ
• Description: IC ARM9 SOC ENH UNIV 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Cpu Speed: 200MHz
• No. Of Timers: 5
• Digital Ic Case Style: BGA
• Supply Voltage Range: 1.65V To 1.94V, 3V To 3.6V
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Case: BGA
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1139

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I
EP93xx User’s Guide
2
S Controller
Tx1_overflow:
Tx2_overflow:
Rx0_underflow:
Rx1_underflow:
Rx2_underflow:
tx0_fifo_full:
tx0_fifo_empty:
tx0_fifo_half_empty:when = 1, FIFO is half empty, otherwise less than half
rx0_fifo_full:
rx0_fifo_empty:
rx0_fifo_half_full: when = 1, FIFO is half full, otherwise less than half full
tx1_fifo_full:
tx1_fifo_empty:
tx1_fifo_half_empty:when = 1, FIFO is half empty, otherwise less than half
rx1_fifo_full:
rx1_fifo_empty:
rx1_fifo_half_full: when = 1, FIFO is half full, otherwise less than half full
tx2_fifo_full:
tx2_fifo_empty:
tx2_fifo_half_empty:when = 1, FIFO is half empty, otherwise less than half
rx2_fifo_full:
Copyright 2007 Cirrus Logic
when = 1, the tx1 FIFO is full and an attempt has been
made to write data to it by the APB or DMA. This bit is
cleared by writing a 0 to it.
when = 1, the tx2 FIFO is full and an attempt has been
made to write data to it by the APB or DMA. This bit is
cleared by writing a 0 to it.
when = 1, the rx0 FIFO is empty and an attempt has been
made to read data from it by the APB or DMA. This bit is
cleared by writing a 0 to it.
when = 1, the rx1 FIFO is empty and an attempt has been
made to read data from it by the APB or DMA. This bit is
cleared by writing a 0 to it.
when = 1, the rx2 FIFO is empty and an attempt has been
made to read data from it by the APB or DMA. This bit is
cleared by writing a 0 to it.
when = 1, FIFO is full, otherwise not full
when = 1, FIFO is empty, otherwise not empty
empty
when = 1, FIFO is full, otherwise not full
when = 1, FIFO is empty, otherwise not empty
when = 1, FIFO is full, otherwise not full
when = 1, FIFO is empty, otherwise not empty
empty
when = 1, FIFO is full, otherwise not full
when = 1, FIFO is empty, otherwise not empty
when = 1, FIFO is full, otherwise not full
when = 1, FIFO is empty, otherwise not empty
empty
when = 1, FIFO is full, otherwise not full
DS785UM1