EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 465
EP9315-CBZ
Manufacturer Part Number
EP9315-CBZ
Description
IC ARM9 SOC ENH UNIV 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9315-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Cpu Speed
200MHz
No. Of Timers
5
Digital Ic Case Style
BGA
Supply Voltage Range
1.65V To 1.94V, 3V To 3.6V
Embedded Interface Type
SPI
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
Case
BGA
Dc
06+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1139
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9315-CBZ
Manufacturer:
CIRRUS
Quantity:
20 000
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HcFmRemaining
DS785UM1
FRT
31
15
Address:
Default:
Definition:
Bit Descriptions:
RSVD
30
14
29
13
28
12
RSVD:
FI:
FSMPS:
FIT:
0x8002_0038
0x0000_0000
Contains the time remaining in the current frame.
RSVD:
FR:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
FrameInterval. This specifies the interval between two
consecutive SOFs in bit times. The nominal value is set to
be 11,999. HCD should store the current value of this field
before resetting HC. By setting the HostControllerReset
field of HcCommandStatus as this will cause the HC to
reset this field to its nominal value. HCD may choose to
restore the stored value upon the completion of the Reset
sequence.
FSLargestDataPacket. This field specifies a value which is
loaded into the Largest Data Packet Counter at the
beginning of each frame. The counter value represents the
largest amount of data in bits which can be sent or
received by the HC in a single transaction at any given
time without causing scheduling overrun. The field value is
calculated by the HCD.
FrameIntervalToggle. HCD toggles this bit whenever it
loads a new value to FrameInterval.
Reserved. Unknown During Read.
FrameRemaining. This counter is decremented at each bit
time. When it reaches zero, it is reset by loading the
FrameInterval value specified in HcFmInterval at the next
bit time boundary. When entering the USBOPERATIONAL
state, HC re-loads the content with the FrameInterval of
HcFmInterval and uses the updated value from the next
SOF.
24
8
RSVD
23
7
FR
22
6
21
5
Universal Serial Bus Host Controller
20
4
19
3
EP93xx User’s Guide
18
2
17
1
11-25
16
0
11
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