AT91M55800A-33CJ Atmel, AT91M55800A-33CJ Datasheet - Page 111

• Manufacturer Part Number: AT91M55800A-33CJ
• Description: IC ARM MCU 16BIT 176BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M55800A-33CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 58
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: EBI, SPI, USART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 58
• Number Of Timers: 10 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91EB55
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 8 bit, 2 Channel
• Cpu Family: AT91
• Device Core: ARM7TDMI
• Device Core Size: 32b
• Frequency (max): 33MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 58
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: BGA
• For Use With: AT91EB55 - KIT EVAL FOR ARM AT91M55800A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.11 Standard Interrupt Sequence
1745F–ATARM–06-Sep-07
It is assumed that:
When NIRQ is asserted, if the bit I of CPSR is 0, the sequence is:
• The Advanced Interrupt Controller has been programmed, AIC_SVR are loaded with
• The Instruction at address 0x18(IRQ exception vector address) is
1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in
2. The ARM Core enters IRQ mode, if it is not already.
3. When the instruction loaded at address 0x18 is executed, the Program Counter is
4. The previous step has effect to branch to the corresponding interrupt service routine.
5. Further interrupts can then be unmasked by clearing the I bit in the CPSR, allowing re-
6. The Interrupt Handler can then proceed as required, saving the registers which are
7. The I bit in the CPSR must be set in order to mask interrupts before exiting, to ensure
8. The End Of Interrupt Command Register (AIC_EOICR) must be written in order to indi-
9. The SPSR (SPSR_irq) is restored. Finally, the saved value of the Link Register is
corresponding interrupt service routine addresses and interrupts are enabled.
ldr pc, [pc, #-&F20]
the IRQ link register (r14_irq) and the Program Counter (r15) is loaded with 0x18. In the
following cycle during fetch at address 0x1C, the ARM Core adjusts r14_irq, decre-
menting it by 4.
loaded with the value read in AIC_IVR. Reading the AIC_IVR has the following effects:
– Set the current interrupt to be the pending one with the highest priority. The current
– De-assert the NIRQ line on the processor. (Even if vectoring is not used, AIC_IVR
– Automatically clear the interrupt, if it has been programmed to be edge-triggered
– Push the current level on to the stack
– Return the value written in the AIC_SVR corresponding to the current interrupt
This should start by saving the Link Register(r14_irq) and the SPSR(SPSR_irq). Note
that the Link Register must be decremented by 4 when it is saved, if it is to be restored
directly into the Program Counter at the end of the interrupt.
assertion of the NIRQ to be taken into account by the core. This can occur if an inter-
rupt with a higher priority than the current one occurs.
used and restoring them at the end. During this phase, an interrupt of priority higher
than the current level will restart the sequence from step 1. Note that if the interrupt is
programmed to be level sensitive, the source of the interrupt must be cleared during
this phase.
that the interrupt is completed in an orderly manner.
cate to the AIC that the current interrupt is finished. This causes the current level to be
popped from the stack, restoring the previous current level if one exists on the stack. If
another interrupt is pending, with lower or equal priority than old current level but with
higher priority than the new current level, the NIRQ line is reasserted, but the interrupt
sequence does not immediately start because the I bit is set in the core.
restored directly into the PC. This has effect of returning from the interrupt to whatever
was being executed before, and of loading the CPSR with the stored SPSR, masking or
unmasking the interrupts depending on the state saved in the SPSR (the previous state
of the ARM Core).
level is the priority level of the current interrupt.
must be read in order to de-assert NIRQ)
AT91M5880A
111