AT91M55800A-33CJ Atmel, AT91M55800A-33CJ Datasheet - Page 247

• Manufacturer Part Number: AT91M55800A-33CJ
• Description: IC ARM MCU 16BIT 176BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M55800A-33CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 58
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: EBI, SPI, USART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 58
• Number Of Timers: 10 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91EB55
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 8 bit, 2 Channel
• Cpu Family: AT91
• Device Core: ARM7TDMI
• Device Core Size: 32b
• Frequency (max): 33MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 58
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: BGA
• For Use With: AT91EB55 - KIT EVAL FOR ARM AT91M55800A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 27-1. NWAIT Rising
1745F–ATARM–06-Sep-07
NWAIT
MCKI
NWAIT Setup before MCKI Rising (EBI
In other cases, the following erroneous behavior occurs:
At maximum speed, asserting the NWAIT in the first access cycle is not possible, as the sum of
the timings “MCKI Falling to Chip Select” and “NWAIT setup to MCKI rising” are generally higher
than one half of a clock period. This leads to using at least one standard wait state. However,
this is not sufficient except to perform byte or half-word read accesses. Word and write accesses
require at least two standard wait states.
The following waveforms further explain the issue:
If the NWAIT setup time is satisfied on the first rising edge of MCKI, the behavior is accurate.
The EBI operations are not affected when the NWAIT rises.
If the NWAIT setup time is satisfied on the following edges of MCKI and if at least one standard
wait state remains to be executed, the behavior is accurate. In the following example, the num-
ber of standard wait states is two. The NWAIT setup time on the second rising edge of MCKI
must be met.
– 32-bit read accesses are not managed correctly and the first 16-bit data sampling
– During write accesses of any type, the NWE rises on the rising edge of the last cycle
takes into account only the standard wait states. 16- and 8-bit accesses are not
affected.
as defined by the programmed number of wait states. However, NWAIT assertion
does affect the length of the total access. Only the NWE pulse length is inaccurate.
5
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AT91M5880A
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