AT91M55800A-33CJ Atmel, AT91M55800A-33CJ Datasheet - Page 114

• Manufacturer Part Number: AT91M55800A-33CJ
• Description: IC ARM MCU 16BIT 176BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M55800A-33CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 58
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: EBI, SPI, USART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 58
• Number Of Timers: 10 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91EB55
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 8 bit, 2 Channel
• Cpu Family: AT91
• Device Core: ARM7TDMI
• Device Core Size: 32b
• Frequency (max): 33MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 58
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: BGA
• For Use With: AT91EB55 - KIT EVAL FOR ARM AT91M55800A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.5
16.6
16.7
114
Interrupts
User Interface
Multi-driver (Open Drain)
AT91M5880A
selected whether the pin is used for its peripheral function or as a parallel I/O line. The register
PIO_IFSR (Input Filter Status) indicates whether or not the filter is activated for each pin.
Each parallel I/O can be programmed to generate an interrupt when a level change occurs. This
is controlled by the PIO_IER (Interrupt Enable) and PIO_IDR (Interrupt Disable) registers which
enable/disable the I/O interrupt by setting/clearing the corresponding bit in the PIO_IMR. When
a change in level occurs, the corresponding bit in the PIO_ISR (Interrupt Status) is set whether
the pin is used as a PIO or a peripheral and whether it is defined as input or output. If the corre-
sponding interrupt in PIO_IMR (Interrupt Mask) is enabled, the PIO interrupt is asserted.
When PIO_ISR is read, the register is automatically cleared.
Each individual I/O is associated with a bit position in the Parallel I/O user interface registers.
Each of these registers are 32 bits wide. If a parallel I/O line is not defined, writing to the corre-
sponding bits has no effect. Undefined bits read zero.
Each I/O can be programmed for multi-driver option. This means that the I/O is configured as
open drain (can only drive a low level) in order to support external drivers on the same pin. An
external pull-up is necessary to guarantee a logic level of one when the pin is not being driven.
Registers PIO_MDER (Multi-driver Enable) and PIO_MDDR (Multi-driver Disable) control this
option. Multi-driver can be selected whether the I/O pin is controlled by the PIO Controller or the
peripheral. PIO_MDSR (Multi-driver Status) indicates which pins are configured to support exter-
nal drivers.
1745F–ATARM–06-Sep-07