AT91M55800A-33CJ Atmel, AT91M55800A-33CJ Datasheet - Page 173

• Manufacturer Part Number: AT91M55800A-33CJ
• Description: IC ARM MCU 16BIT 176BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M55800A-33CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 58
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: EBI, SPI, USART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 58
• Number Of Timers: 10 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91EB55
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 8 bit, 2 Channel
• Cpu Family: AT91
• Device Core: ARM7TDMI
• Device Core Size: 32b
• Frequency (max): 33MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 58
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: BGA
• For Use With: AT91EB55 - KIT EVAL FOR ARM AT91M55800A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.5
TC Block 0 Base Address:
TC Block 1 Base Address:
Table 19-2.
TC_BCR (Block Control Register) and TC_BMR (Block Mode Register) control the TC block. TC Channels are controlled
by the registers listed in Table 19-3. The offset of each of the Channel registers in Table 19-3 is in relation to the offset of
the corresponding channel as mentioned in Table 19-2.
Table 19-3.
Note:
1745F–ATARM–06-Sep-07
Offset
Offset
0xC0
0xC4
0x0C
0x1C
0x2C
0x00
0x40
0x80
0x00
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
TC User Interface
1. Read-only if WAVE = 0
TC Global Register Mapping
TC Channel Register Mapping
Channel/Register
TC Channel 0
TC Channel 1
TC Channel 2
TC Block Control Register
TC Block Mode Register
Register
Channel Control Register
Channel Mode Register
Reserved
Reserved
Counter Value
Register A
Register B
Register C
Status Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
0xFFFD0000 (Code Label TCB0_BASE)
0xFFFD4000 (Code Label TCB1_BASE)
TC_BMR
TC_CMR
TC_BCR
TC_CCR
TC_IMR
TC_IDR
TC_IER
TC_RC
TC_CV
TC_RA
TC_RB
TC_SR
Name
Name
See
See
See
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Access
Access
Table 19-3
Table 19-3
Table 19-3
AT91M5880A
(1)
(1)
Reset State
Reset State
–
0
–
0
–
–
0
0
0
0
–
–
–
0
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