AT91M55800A-33CJ Atmel, AT91M55800A-33CJ Datasheet - Page 56

• Manufacturer Part Number: AT91M55800A-33CJ
• Description: IC ARM MCU 16BIT 176BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M55800A-33CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 58
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: EBI, SPI, USART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 58
• Number Of Timers: 10 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91EB55
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 8 bit, 2 Channel
• Cpu Family: AT91
• Device Core: ARM7TDMI
• Device Core Size: 32b
• Frequency (max): 33MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 58
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: BGA
• For Use With: AT91EB55 - KIT EVAL FOR ARM AT91M55800A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.3
12.3.1
12.3.2
56
Clock Generator
AT91M5880A
Main Oscillator
Phase Lock Loop
The clock generator consists of the main oscillator, the PLL and the clock selection logic with its
prescaler. It aims at selecting the Master Clock, called MCK throughout this datasheet. The
clock generator also contains the circuitry needed to drive the MCKO pin with the master clock
signal.
The Main Oscillator is designed for a 3 to 20 MHz fundamental crystal. The typical crystal con-
nection is illustrated in
frequencies lower than 8 MHz. The oscillator contains 25 pF capacitances on each XIN and
XOUT pin. Consequently, CL1 and CL2 can be removed when a crystal with a load capacitance
of 12.5 pF is used.
Figure 12-4. Typical Crystal Connection of Main Oscillator
The Main Oscillator can be bypassed if the MOSCBYP bit in the Clock Generator Mode Register
(APMC_CGMR) is set to 1. In this case, any frequency (up to the maximum specified in the elec-
trical characteristics datasheet) can be input on the XIN pin. If the PLL is used, a minimum input
frequency is required.
To minimize the power required to start up the system, the Main Oscillator is disabled after the
reset. The software can deactivate the Main Oscillator to reduce the power consumption by
clearing the MOSCEN bit in APMC_CGMR. The MOSCS (Main Oscillator Status) bit in
APMC_SR is automatically cleared, indicating that the Main Oscillator is off.
Writing the MOSCEN bit in APMC_CGMR reactivates the Main Oscillator and loads the value
written in the OSCOUNT field in APMC_CGMR in the oscillator counter. Then, the oscillator
counter decrements every 8 clock cycles and when it reaches 0, the MOSCS bit is set and can
provide an interrupt.
The Main Oscillator output signal feeds the phase lock loop, which aims at multiplying the fre-
quency of its input signal by a number up to 64. This number is programmed in the MUL field of
APMC_CGMR and the multiplication ratio is the programmed value plus one (MUL+1). If a null
value is programmed into MUL, the PLL is automatically disabled to save power.
The PLL is disabled at reset to minimize the power consumption.
A start-up sequence must be executed to enable the PLL if it is disabled. This sequence is
started by writing a new MUL value in APMC_CGMR. This automatically clears the LOCK bit in
APMC_SR and loads the PLL counter with the value programmed in the PLLCOUNT field. Then,
the PLL counter decrements at each Slow Clock cycle.
Figure
C
L1
XIN
12-4. The 1 kΩ resistor is only required for crystals with
C
1K
L2
XOUT
GNDPLL
1745F–ATARM–06-Sep-07