AT91M55800A-33CJ Atmel, AT91M55800A-33CJ Datasheet - Page 58

• Manufacturer Part Number: AT91M55800A-33CJ
• Description: IC ARM MCU 16BIT 176BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M55800A-33CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 58
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: EBI, SPI, USART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 58
• Number Of Timers: 10 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91EB55
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 8 bit, 2 Channel
• Cpu Family: AT91
• Device Core: ARM7TDMI
• Device Core Size: 32b
• Frequency (max): 33MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 58
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: BGA
• For Use With: AT91EB55 - KIT EVAL FOR ARM AT91M55800A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.3.5
12.3.6
12.3.7
58
AT91M5880A
Slow Clock Interrupt
Prescaler
Master Clock Output
Figure 12-6. Clock Switch
The APMC also features the Slow Clock interrupt, allowing the user to detect when the Master
Clock is actually switched to the Slow Clock. Switching from the Slow Clock to a higher fre-
quency is generally performed safely, as the processor is running slower than the target
frequency. However, switching from a high frequency to the Slow Clock requires the high fre-
quency to be valid during the switch time. The Slow Clock interrupt permits the user to know
exactly when the switch has been achieved, thus, when the Main Oscillator or the PLL can be
disabled.
The prescaler is the last stage to provide the master clock. It permits the selected clock to be
divided by a power of 2 between 1 and 64. The default value is 1 after the reset. The prescaler
allows the microcontroller operating frequency to reach down to 512 Hz.
Precautions must be taken when defining a master clock lower than the Slow Clock, as some
peripherals (RTC and APMC) can still operate at Slow Clock frequency. In this case, access to
the peripheral registers that are updated at 32 kHz cannot be ensured.
The Master Clock can be output to the MCKO pad. The MCKO pad can be tri-stated to minimize
power consumption by setting the bit MCKODS (Master Clock Output Disable) in APMC_CGMR
(default is MCKO enabled).
PLL Clock Mode
3 PLL Clock Cycles
5 SLCK Cycles
7 SLCK Cycles
+
3 PLL Clock Cycles
4 SLCK Cycles
Slow Clock Mode
3 Oscillator Clock Cycles
+
3 PLL Clock Cycles
4 SLCK Cycles
5 SLCK Cycles
+
+
3 Oscillator Clock Cycles
3 SLCK Cycles
+
Oscillator Clock Mode
5 SLCK Cycles
1745F–ATARM–06-Sep-07