AT91M55800A-33CJ Atmel, AT91M55800A-33CJ Datasheet - Page 98

• Manufacturer Part Number: AT91M55800A-33CJ
• Description: IC ARM MCU 16BIT 176BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M55800A-33CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 58
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: EBI, SPI, USART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 58
• Number Of Timers: 10 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91EB55
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 8 bit, 2 Channel
• Cpu Family: AT91
• Device Core: ARM7TDMI
• Device Core Size: 32b
• Frequency (max): 33MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 58
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: BGA
• For Use With: AT91EB55 - KIT EVAL FOR ARM AT91M55800A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.1
15.2
15.3
98
Hardware Interrupt Vectoring
Priority Controller
Interrupt Handling
AT91M5880A
The hardware interrupt vectoring reduces the number of instructions to reach the interrupt han-
dler to only one. By storing the following instruction at address 0x00000018, the processor loads
the program counter with the interrupt handler address stored in the AIC_IVR register. Execution
is then vectored to the interrupt handler corresponding to the current interrupt.
The current interrupt is the interrupt with the highest priority when the Interrupt Vector Register
(AIC_IVR) is read. The value read in the AIC_IVR corresponds to the address stored in the
Source Vector Register (AIC_SVR) of the current interrupt. Each interrupt source has its corre-
sponding AIC_SVR. In order to take advantage of the hardware interrupt vectoring it is
necessary to store the address of each interrupt handler in the corresponding AIC_SVR, at sys-
tem initialization.
The NIRQ line is controlled by an 8-level priority encoder. Each source has a programmable pri-
ority level of 7 to 0. Level 7 is the highest priority and level 0 the lowest.
When the AIC receives more than one unmasked interrupt at a time, the interrupt with the high-
est priority is serviced first. If both interrupts have equal priority, the interrupt with the lowest
interrupt source number (see Table
The current priority level is defined as the priority level of the current interrupt at the time the reg-
ister AIC_IVR is read (the interrupt which is serviced).
In the case when a higher priority unmasked interrupt occurs while an interrupt already exists,
there are two possible outcomes depending on whether the AIC_IVR has been read.
When the end of interrupt command register (AIC_EOICR) is written the current interrupt level is
updated with the last stored interrupt level from the stack (if any). Hence at the end of a higher
priority interrupt, the AIC returns to the previous state corresponding to the preceding lower pri-
ority interrupt which had been interrupted.
The interrupt handler must read the AIC_IVR as soon as possible. This de-asserts the NIRQ
request to the processor and clears the interrupt in case it is programmed to be edge-triggered.
This permits the AIC to assert the NIRQ line again when a higher priority unmasked interrupt
occurs.
At the end of the interrupt service routine, the end of interrupt command register (AIC_EOICR)
must be written. This allows pending interrupts to be serviced.
• If the NIRQ line has been asserted but the AIC_IVR has not been read, then the processor
• If the processor has already read the AIC_IVR then the NIRQ line is reasserted. When the
reads the new higher priority interrupt handler address in the AIC_IVR register and the
current interrupt level is updated.
processor has authorized nested interrupts to occur and reads the AIC_IVR again, it reads
the new, higher priority interrupt handler address. At the same time the current priority value
is pushed onto a first-in last-out stack and the current priority is updated to the higher priority.
ldr PC,[PC,# -&F20]
Table
15-1) is serviced first.
1745F–ATARM–06-Sep-07