AT91M55800A-33CJ Atmel, AT91M55800A-33CJ Datasheet - Page 14

• Manufacturer Part Number: AT91M55800A-33CJ
• Description: IC ARM MCU 16BIT 176BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M55800A-33CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 58
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: EBI, SPI, USART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 58
• Number Of Timers: 10 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91EB55
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 8 bit, 2 Channel
• Cpu Family: AT91
• Device Core: ARM7TDMI
• Device Core Size: 32b
• Frequency (max): 33MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 58
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: BGA
• For Use With: AT91EB55 - KIT EVAL FOR ARM AT91M55800A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.3
7.4
7.4.1
7.4.2
14
Master Clock
Reset
AT91M5880A
NRST Pin
NTRST Pin
Master Clock is generated in one of the following ways, depending on programming in the
APMC registers:
The Master Clock (MCK) is also provided as an output of the device on the pin MCKO, whose
state is controlled by the APMC module.
Reset restores the default states of the user interface registers (defined in the user interface of
each peripheral), and forces the ARM7TDMI to perform the next instruction fetch from address
zero. Aside from the program counter, the ARM7TDMI registers do not have defined reset
states.
NRST is active low-level input. It is asserted asynchronously, but exit from reset is synchronized
internally to the MCK. At reset, the source of MCK is the Slow Clock (32768 Hz crystal), and the
signal presented on MCK must be active within the specification for a minimum of 10 clock
cycles up to the rising edge of NRST, to ensure correct operation.
Test Access Port (TAP) reset functionality is provided through the NTRST signal.
The NTRST control pin initializes the selected TAP controller. The TAP controller involved in this
reset is determined according to the initial logical state applied on the JTAGSEL pin after the last
valid NRST.
In either Boundary Scan or ICE Mode a reset can be performed from the same or different cir-
cuitry, as shown in
asserted after each power-up. (See the AT91M55800A electrical datasheet, Atmel lit° 1727, for
the necessary minimum pulse assertion time.)
Figure 7-1.
Notes:
• From the 32768 Hz low-power oscillator that clocks the RTC
• The on-chip main oscillator together with a PLL generate a software-programmable main
clock in the 500 Hz to 33 MHz range. The main oscillator can be bypassed to allow the user
to enter an external clock signal.
Controller
Controller
1. NRST and NTRST handling in Debug Mode during development.
2. NRST and NTRST handling during production.
Reset
Reset
Separate or Common Reset Management
Figure 7-1
NTRST
NRST
AT91M55800A
below. But in all cases, the NTRST like the NRST signal, must be
(1)
Controller
Reset
NTRST
NRST
AT91M55800A
1745F–ATARM–06-Sep-07
(2)